Abstract: A method for implementing an inductor-capacitor filter in an integrated circuit. Embodiments of the invention implement a 5-pole LC low-pass filter suitable for incorporation in wireless applications necessitating compact layouts. Inductors are formed in an IC as concentric coils on metallization layers, the concentric coils providing a negative coupling coefficient between the inductors. The invention provides programmable frequency response characteristics, enabling the transmission of high-frequency base band information while attenuating carrier RF frequencies.

Abstract: A method for controlling capacitance associated with solder sphere bumps is provided. An improved structure is proposed which uses a much smaller pad on an IC with standard chip dielectric and passivation layers. An additional thick dielectric layer is then applied to the structure and a small via is opened in this thick dielectric layer. An under bump metal (UBM) is deposited and defined to provide a chip to solder sphere bump interface and an electrical connection between the pad and the solder sphere bump. The solder sphere bump can then be attached and reflowed to the UBM. Practical implementations of the invention typically obtain factors of reduction in capacitance of at least 10-20.

Abstract: A method for implementing an inductor-capacitor filter in an integrated circuit. Embodiments of the invention implement a 5-pole LC low-pass filter suitable for incorporation in wireless applications necessitating compact layouts. Inductors are formed in an IC as concentric coils on metallization layers, the concentric coils providing a negative coupling coefficient between the inductors. The invention provides programmable frequency response characteristics, enabling the transmission of high-frequency base band information while attenuating carrier RF frequencies.

Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage as well as stabilizing capacitors for stabilizing control node voltages.

Abstract: An active termination circuit having a selective DC power consumption for clamping signals on a bus in an electronic device is described. The active termination circuit is configured to clamp the signals on the bus to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes bottom clamping transistors coupled to a first potential having bottom clamping transistor control nodes arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes top clamping transistors coupled to a second potential having top clamping transistor control nodes arranged for clamping the signal at about a second reference voltage. The circuit also has a variable current supply coupled to said first threshold reference transistor and said second threshold reference transistor arranged to reduce the DC power consumption of the active termination circuit as needed.

Abstract: An active termination circuit for clamping signals on a bus in an electronic device is described. The active termination circuit is configured to clamp the signals on the bus to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes bottom clamping transistors coupled to a first potential having bottom clamping transistor control nodes arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes top clamping transistors coupled to a second potential having top clamping transistor control nodes arranged for clamping the signal at about a second reference voltage.

Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage.

Abstract: An active termination circuit having localized potential supplies for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first localized potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second localized potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage.

Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device in a tri-state mode is described. The active circuit includes a tri-state output buffer and a bottom clamping transistor coupled to GND and the tri-state output buffer having a bottom clamping transistor control node arranged for clamping the signal at about GND. A bottom threshold reference transistor coupled to a first reference voltage supply configured to supply a first reference voltage. The bottom threshold reference transistor provides a first bias voltage to the bottom clamping transistor control node that biases the bottom clamping transistor control node at about a first threshold voltage above GND where the first threshold voltage represents a threshold voltage of the bottom clamping transistor.

Abstract: An active termination circuit for protecting a node against an ESD voltage spike is described. The ESD protection circuit includes a bottom ESD protection transistor having a first node coupled to a first potential and a bottom ESD protection transistor intrinsic diode reverse biasedly coupling said node to a first reference voltage supply and a bottom threshold reference transistor coupled to the first reference voltage supply. The bottom threshold reference transistor provides a first bias voltage to the bottom ESD protection transistor gate that biases the bottom clamping transistor gate at about a first threshold voltage from the first reference voltage representing a threshold voltage of said bottom ESD protection transistor.

Abstract: An active termination circuit for terminating a transmission line in bused or networked device, which might include a plurality of devices. The active termination circuit is configured to clamp a voltage level on the transmission line to one of a first reference voltage level and a second reference voltage level. The active termination circuit includes a first clamping transistor coupled to a transmission line terminal and a first terminal. The transmission line terminal is configured to be coupled to the transmission line in the electronic device. The first terminal is configured to be coupled to the first reference voltage level in the electronic device. There is included a second clamping transistor coupled to the transmission line terminal and a second terminal. The second terminal is configured to be coupled to the second reference voltage level in the electronic device. There is also included a first threshold reference device coupled to the first clamping transistor.

Abstract: An integrated electrical overload protection device and method of formation which functions as a thermal fuse. The device is integrated directly on the underlying structural or foundational material of an electrical circuit which experiences the electrical overstress. The device can be formed according to standard semiconductor process steps when formed on a semiconductor substrate. The device, or fuse, includes a first and second contact area separated by a gap area. A least a portion of the upper surfaces of the contact areas are covered with a wettable material such as gold. A solder bump, or bridge, is applied which spans the contact areas and provides an closed electrical connection. Upon application of an overload condition across the bridge material, a rise in temperature causes the solder material to melt. The solder flows onto the wettable areas and is drawn out of the gap area to thereby disrupt the electrical connection between the contact areas.

Abstract: An active termination circuit for terminating a transmission line in memory bus, which might include a plurality of devices. The active termination circuit is configured to clamp a voltage level on the transmission line to one of a first reference voltage level and a second reference voltage level. The active termination circuit includes a first clamping transistor coupled to a transmission line terminal and a first terminal. The transmission line terminal is configured to be coupled to the transmission line in the electronic device. The first terminal is configured to be coupled to the first reference voltage level in the electronic device. There is included a second clamping transistor coupled to the transmission line terminal and a second terminal. The second terminal is configured to be coupled to the second reference voltage level in the electronic device. There is also included a first threshold reference device coupled to the first clamping transistor.

Abstract: An active termination circuit for terminating a transmission line in an electronic device. The active termination circuit is configured to clamp a voltage level on the transmission line to one of a first reference voltage level and a second reference voltage level. The active termination circuit includes a first clamping transistor coupled to a transmission line terminal and a first terminal. The transmission line terminal is configured to be coupled to the transmission line in the electronic device. The first terminal is configured to be coupled to the first reference voltage level in the electronic device. There is included a second clamping transistor coupled to the transmission line terminal and a second terminal. The second terminal is configured to be coupled to the second reference voltage level in the electronic device. There is also included a first threshold reference device coupled to the first clamping transistor.