Abstract: A method for porting an existing vehicle control software developed for a single-core control device into a modified multi-core control software or for converting an existing vehicle control software into an optimized multi-core control software is provided. The existing control software comprises numerous repeatedly executable runnables. Information is exchanged between the runnables through writing and reading of communication variables. A modified information exchange via time implicit communication is provided for parallelized runnables in the multi-core control software that is generated by the method. The method includes: analysis of the existing control software regarding a writer-to-reader cardinality of the information exchange with respect to a communication variable; and defining an implementation of the time implicit communication as a function of the determined writer-to-reader cardinality.

Abstract: A microprocessor for a vehicle control device includes: an instruction set; a register section with a status register, a first flag being provided in the status register for storing a logical result of a comparison operation; and an arithmetic logical unit. The status register comprises a second flag for storing the logical result of a second comparison operation. The instruction set comprises a first additional instruction, which performs a comparison among two handed-over operands, a result of the comparison being stored in the second flag. The instruction set comprises a second additional instruction, which selects and performs one of at least three pre-defined operations on a basis of a logic connection of values in the first flag and the second flag, for updating an upper boundary and/or a lower boundary of a search field in a binary search for a next iteration.

Abstract: A method for porting an existing vehicle control software developed for a single-core control device into a modified multi-core control software or for converting an existing vehicle control software into an optimized multi-core control software is provided. The existing control software comprises numerous repeatedly executable runnables. Information is exchanged between the runnables through writing and reading of communication variables. A modified information exchange via time implicit communication is provided for parallelized runnables in the multi-core control software that is generated by the method. The method includes: analysis of the existing control software regarding a writer-to-reader cardinality of the information exchange with respect to a communication variable; and defining an implementation of the time implicit communication as a function of the determined writer-to-reader cardinality.

Abstract: A microprocessor for a vehicle control device includes: an instruction set; a register section with a status register, a first flag being provided in the status register for storing a logical result of a comparison operation; and an arithmetic logical unit. The status register comprises a second flag for storing the logical result of a second comparison operation. The instruction set comprises a first additional instruction, which performs a comparison among two handed-over operands, a result of the comparison being stored in the second flag. The instruction set comprises a second additional instruction, which selects and performs one of at least three pre-defined operations on a basis of a logic connection of values in the first flag and the second flag, for updating an upper boundary and/or a lower boundary of a search field in a binary search for a next iteration.

Abstract: A data processing device is described with a memory and a first and a second data processing component. The first data processing component comprises a control memory comprising, for each memory region of a plurality of memory regions of the memory, an indication whether a data access to the memory region may be carried out by the first data processing component and a data access circuit configured to carry out a data access to a memory region of the plurality of memory regions if a data access to the memory region may be carried out by the first data processing component; and a setting circuit configured to set the indication for a memory region to indicate that a data access to the memory region may not be carried out by the first data processing component in response to the completion of a data access of the first data processing component to the memory region.

Abstract: A data processing device is described with a memory and a first and a second data processing component. The first data processing component comprises a control memory comprising, for each memory region of a plurality of memory regions of the memory, an indication whether a data access to the memory region may be carried out by the first data processing component and a data access circuit configured to carry out a data access to a memory region of the plurality of memory regions if a data access to the memory region may be carried out by the first data processing component; and a setting circuit configured to set the indication for a memory region to indicate that a data access to the memory region may not be carried out by the first data processing component in response to the completion of a data access of the first data processing component to the memory region.