Abstract: Disclosed is a reconfigurable complementary metal oxide semiconductor (CMOS) device with multiple operating modes (e.g., frequency multiplication mode, etc.). The device includes an N-type field effect transistor (NFET) and a P-type field effect transistor (PFET), which are threshold voltage-programmable, which are connected in parallel, and which have electrically connected gates. The threshold voltages of the NFET and PFET can be concurrently programmed and the operating mode of the device can be set depending upon the specific combination of threshold voltages achieved in the NFET and PFET. Optionally, the threshold voltages of the NFET and PFET can be concurrently reprogrammed to switch the operating mode. Such a device is relatively small and achieves frequency multiplication and other functions with minimal power consumption. Also disclosed are methods for forming the device and for reconfiguring the device (i.e., for concurrently programming the NFET and PFET to set or switch operating modes).

Abstract: Disclosed is a reconfigurable complementary metal oxide semiconductor (CMOS) device with multiple operating modes (e.g., frequency multiplication mode, etc.). The device includes an N-type field effect transistor (NFET) and a P-type field effect transistor (PFET), which are threshold voltage-programmable, which are connected in parallel, and which have electrically connected gates. The threshold voltages of the NFET and PFET can be concurrently programmed and the operating mode of the device can be set depending upon the specific combination of threshold voltages achieved in the NFET and PFET. Optionally, the threshold voltages of the NFET and PFET can be concurrently reprogrammed to switch the operating mode. Such a device is relatively small and achieves frequency multiplication and other functions with minimal power consumption. Also disclosed are methods for forming the device and for reconfiguring the device (i.e., for concurrently programming the NFET and PFET to set or switch operating modes).

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a layout optimization for radio frequency (RF) device performance and methods of manufacture. The structure includes: a first active device on a substrate; source and drain diffusion regions adjacent to the first active device; and a first contact in electrical contact with the source and drain diffusion regions and which is spaced away from the first active device to optimize a stress component in a channel region of the first active device.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a layout optimization for radio frequency (RF) device performance and methods of manufacture. The structure includes: a first active device on a substrate; source and drain diffusion regions adjacent to the first active device; and a first contact in electrical contact with the source and drain diffusion regions and which is spaced away from the first active device to optimize a stress component in a channel region of the first active device.

Abstract: Disclosed is a reconfigurable complementary metal oxide semiconductor (CMOS) device with multiple operating modes (e.g., frequency multiplication mode, etc.). The device includes an N-type field effect transistor (NFET) and a P-type field effect transistor (PFET), which are threshold voltage-programmable, which are connected in parallel, and which have electrically connected gates. The threshold voltages of the NFET and PFET can be concurrently programmed and the operating mode of the device can be set depending upon the specific combination of threshold voltages achieved in the NFET and PFET. Optionally, the threshold voltages of the NFET and PFET can be concurrently reprogrammed to switch the operating mode. Such a device is relatively small and achieves frequency multiplication and other functions with minimal power consumption. Also disclosed are methods for forming the device and for reconfiguring the device (i.e., for concurrently programming the NFET and PFET to set or switch operating modes).

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a layout optimization for radio frequency (RF) device performance and methods of manufacture. The structure includes: a first active device on a substrate; source and drain diffusion regions adjacent to the first active device; and a first contact in electrical contact with the source and drain diffusion regions and which is spaced away from the first active device to optimize a stress component in a channel region of the first active device.