Patents by Inventor Dominik Olligs
Dominik Olligs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9589854Abstract: The present disclosure provides in various aspects an alignment monitoring structure and method for monitoring the alignment between a target gate conductor and the corresponding target contact in a semiconductor device, for example, in a CMOS. In accordance with some illustrative embodiments herein, a structure with a plurality of gate conductors disposed over the substrate so as to define a row of parallel gate conductors and a plurality of first contacts is provided, wherein each of the first contacts is disposed between two adjacent gate conductors so as to define a first lateral distance between a first gate conductor and the first contact and a second lateral distance between the first contact and a second gate conductor, and wherein the first lateral distance and the second lateral distance vary systematically along the row of parallel gate conductors.Type: GrantFiled: May 12, 2015Date of Patent: March 7, 2017Assignee: GLOBALFOUNDRIES Inc.Inventor: Dominik Olligs
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Publication number: 20160336240Abstract: The present disclosure provides in various aspects an alignment monitoring structure and method for monitoring the alignment between a target gate conductor and the corresponding target contact in a semiconductor device, for example, in a CMOS. In accordance with some illustrative embodiments herein, a structure with a plurality of gate conductors disposed over the substrate so as to define a row of parallel gate conductors and a plurality of first contacts is provided, wherein each of the first contacts is disposed between two adjacent gate conductors so as to define a first lateral distance between a first gate conductor and the first contact and a second lateral distance between the first contact and a second gate conductor, and wherein the first lateral distance and the second lateral distance vary systematically along the row of parallel gate conductors.Type: ApplicationFiled: May 12, 2015Publication date: November 17, 2016Inventor: Dominik Olligs
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Patent number: 9196684Abstract: A method of reducing the impact of FEoL topography on dual stress liner depositions and the resulting device are disclosed. Embodiments include forming a first nitride layer between and over a pFET and an nFET; thinning the first nitride layer; forming a second nitride layer over the first nitride layer; and removing the first and the second nitride layers from over the pFET.Type: GrantFiled: April 16, 2014Date of Patent: November 24, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Kai Frohberg, Peter Moll, Dominik Olligs, Heike Scholz
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Publication number: 20150303261Abstract: A method of reducing the impact of FEoL topography on dual stress liner depositions and the resulting device are disclosed. Embodiments include forming a first nitride layer between and over a pFET and an nFET; thinning the first nitride layer; forming a second nitride layer over the first nitride layer; and removing the first and the second nitride layers from over the pFET.Type: ApplicationFiled: April 16, 2014Publication date: October 22, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Kai FROHBERG, Peter MOLL, Dominik OLLIGS, Heike SCHOLZ
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Patent number: 8941182Abstract: Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein electrical interconnects between circuit elements based on a buried sublevel metallization may provide improved transistor density. One illustrative method disclosed herein includes forming a contact dielectric layer above first and second transistor elements of a semiconductor device, and after forming the contact dielectric layer, forming a buried conductive element below an upper surface of the contact dielectric layer, the conductive element providing an electrical connection between the first and second transistor elements.Type: GrantFiled: June 7, 2011Date of Patent: January 27, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Kai Frohberg, Dominik Olligs, Jens Heinrich, Katrin Reiche
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Patent number: 8492217Abstract: Disclosed herein are various methods of forming conductive contacts with reduced dimensions and various semiconductor devices incorporating such conductive contacts. In one example, one method disclosed herein includes forming a layer of insulating material above a semiconducting substrate, wherein the layer of material has a first thickness, forming a plurality of contact openings in the layer of material having the first thickness and forming an organic material in at least a portion of each of the contact openings. This illustrative method further includes the steps of, after forming the organic material, performing an etching process to reduce the first thickness of the layer of insulating material to a second thickness that is less than the first thickness, after performing the etching process, removing the organic material from the contact openings and forming a conductive contact in each of the contact openings.Type: GrantFiled: September 20, 2011Date of Patent: July 23, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Kai Frohberg, Dominik Olligs, Daniel Prochnow, Katrin Reiche
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Publication number: 20130072016Abstract: Disclosed herein are various methods of forming conductive contacts with reduced dimensions and various semiconductor devices incorporating such conductive contacts. In one example, one method disclosed herein includes forming a layer of insulating material above a semiconducting substrate, wherein the layer of material has a first thickness, forming a plurality of contact openings in the layer of material having the first thickness and forming an organic material in at least a portion of each of the contact openings. This illustrative method further includes the steps of, after forming the organic material, performing an etching process to reduce the first thickness of the layer of insulating material to a second thickness that is less than the first thickness, after performing the etching process, removing the organic material from the contact openings and forming a conductive contact in each of the contact openings.Type: ApplicationFiled: September 20, 2011Publication date: March 21, 2013Applicant: GLOBALFOUNDRIES Inc.Inventors: Kai Frohberg, Dominik Olligs, Daniel Prochnow, Katrin Reiche
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Publication number: 20120313176Abstract: Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein electrical interconnects between circuit elements based on a buried sublevel metallization may provide improved transistor density. One illustrative method disclosed herein includes forming a contact dielectric layer above first and second transistor elements of a semiconductor device, and after forming the contact dielectric layer, forming a buried conductive element below an upper surface of the contact dielectric layer, the conductive element providing an electrical connection between the first and second transistor elements.Type: ApplicationFiled: June 7, 2011Publication date: December 13, 2012Applicant: GLOBALFOUNDRIES INC.Inventors: Kai Frohberg, Dominik Olligs, Jens Heinrich, Katrin Reiche
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Patent number: 8021933Abstract: A method of forming an integrated circuit includes forming first structures in a first portion of the integrated circuit and forming second structures, which are arranged more densely than the first structures, in a second portion. The first and second structures are defined by lithography processes using photomasks. At least one of the photomasks includes both openings in a first region for supporting the definition of the first structures and openings in a second region for supporting the definition of the second structures.Type: GrantFiled: August 29, 2007Date of Patent: September 20, 2011Assignee: Qimonda AGInventors: Dominik Olligs, Joachim Deppe, David Pritchard, Christoph Kleint
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Patent number: 8009477Abstract: An integrated circuit and a method of forming an integrated circuit. One embodiment includes a conductive line formed above a surface of a carrier. A slope of the sidewalls of the conductive line in a direction perpendicular to the surface of the carrier reveals a discontinuity and a width of the conductive line in an upper portion thereof is larger than the corresponding width in the lower portion.Type: GrantFiled: July 30, 2008Date of Patent: August 30, 2011Assignee: Qimonda AGInventors: Christoph Kleint, Nicolas Nagel, Dominik Olligs, Matthias Markert
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Patent number: 7935608Abstract: A method for manufacturing an integrated circuit including at least one storage cell is provided. The method includes providing a substrate having a first and second side, and a plurality of parallel trenches so that a dividing wall is formed between adjacent trenches, filling the trenches with an insulating compound, providing a first insulating layer having a first and second side on the top surface of the dividing wall, wherein the first side is arranged on the substrate's first side, providing a first conductive layer having a first and second side, wherein the first side is arranged on the insulating layer's second side, wherein the conductive layer protrudes from the substrate surface, providing a second conductive layer having a first and second side, wherein the first side is located on the first conductive layer's second side, and removing parts of the second conductive layer by an anisotropic etching means.Type: GrantFiled: June 2, 2008Date of Patent: May 3, 2011Assignee: Qimonda AGInventors: Frank Heinrichsdorff, Nicolas Nagel, Jens-Uwe Sachse, Andreas Voerckel, Dominik Olligs, Torsten Mueller
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Patent number: 7733698Abstract: A memory device having an array portion including memory cells, and a peripheral portion including conductive lines is disclosed. In one embodiment, portions of the conductive lines adjoin a surface of a semiconductor carrier.Type: GrantFiled: March 21, 2007Date of Patent: June 8, 2010Assignee: Qimonda AGInventors: Joachim Deppe, Dominik Olligs, Christoph Kleint, Eike Ruttkowski, Ricardo Mikalo
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Publication number: 20100027311Abstract: An integrated circuit and a method of forming an integrated circuit. One embodiment includes a conductive line formed above a surface of a carrier. A slope of the sidewalls of the conductive line in a direction perpendicular to the surface of the carrier reveals a discontinuity and a width of the conductive line in an upper portion thereof is larger than the corresponding width in the lower portion.Type: ApplicationFiled: July 30, 2008Publication date: February 4, 2010Applicant: QIMONDA AGInventors: Christoph Kleint, Nicolas Nagel, Dominik Olligs, Matthias Markert
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Patent number: 7642158Abstract: The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.Type: GrantFiled: September 30, 2005Date of Patent: January 5, 2010Assignee: Infineon Technologies AGInventors: Stefano Parascandola, Roman Knoefler, Stephan Riedel, Dominik Olligs, Torsten Mueller, Dirk Caspary
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Publication number: 20090294825Abstract: A method for manufacturing an integrated circuit including at least one storage cell is provided. The method includes providing a substrate having a first and second side, and a plurality of parallel trenches so that a dividing wall is formed between adjacent trenches, filling the trenches with an insulating compound, providing a first insulating layer having a first and second side on the top surface of the dividing wall, wherein the first side is arranged on the substrate's first side, providing a first conductive layer having a first and second side, wherein the first side is arranged on the insulating layer's second side, wherein the conductive layer protrudes from the substrate surface, providing a second conductive layer having a first and second side, wherein the first side is located on the first conductive layer's second side, and removing parts of the second conductive layer by an anisotropic etching means.Type: ApplicationFiled: June 2, 2008Publication date: December 3, 2009Inventors: Frank Heinrichsdorff, Nicolas Nagel, Jens-Uwe Sachse, Andreas Voerckel, Dominik Olligs, Torsten Mueller
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Publication number: 20090242955Abstract: An integrated circuit includes: a contact structure with a first stack of at least two conductive layers, and a gate electrode with a second stack of conductive layers, the second stack of layers having the same sequence of conductive layers as the first stack.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Applicant: QIMONDA AGInventor: Dominik Olligs
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Patent number: 7589019Abstract: A memory cell array includes a plurality of first conductive lines running in a first direction, where the first conductive lines have a pitch Bp, a plurality of second conductive lines, and a plurality of memory cells. Each of the memory cells are at least partially formed in a semiconductor substrate and are accessible by addressing at least a corresponding one of the first conductive lines and at least a corresponding one of the second conductive lines. The memory cell array further includes a plurality of supporting lines, where the supporting lines have a pitch Mp and are disposed above the first and second conductive lines, and a plurality of supporting contacts. The first conductive lines are connected with corresponding ones of the supporting lines via the supporting contacts, and Mp is larger than Bp.Type: GrantFiled: May 31, 2006Date of Patent: September 15, 2009Assignee: Infineon Technologies, AGInventors: Dominik Olligs, Veronika Polei
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Patent number: 7531867Abstract: The invention in one of the embodiments refers to a method for forming an integrated memory device, the method including a forming a plurality of bitlines, wherein forming the plurality of bitlines includes forming diffusion lines in a substrate, forming an electrically conductive silicidation barrier layer on a substrate surface exposed, and depositing a conductive layer comprising a metal on the silicidation barrier layer.Type: GrantFiled: March 27, 2006Date of Patent: May 12, 2009Assignee: Infineon Technologies AGInventor: Dominik Olligs
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Patent number: 7521351Abstract: A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional “contact to interconnect” structures.Type: GrantFiled: June 30, 2005Date of Patent: April 21, 2009Assignee: Infineon Technologies AGInventors: Thomas Mikolajick, Torsten Mueller, Nicolas Nagel, Lars Bach, Dominik Olligs, Veronika Polei
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Publication number: 20090057743Abstract: A method of forming an integrated circuit includes forming first structures in a first portion of the integrated circuit and forming second structures, which are arranged more densely than the first structures, in a second portion. The first and second structures are defined by lithography processes using photomasks. At least one of the photomasks includes both openings in a first region for supporting the definition of the first structures and openings in a second region for supporting the definition of the second structures.Type: ApplicationFiled: August 29, 2007Publication date: March 5, 2009Applicant: QIMONDA AGInventors: Dominik Olligs, Joachim Deppe, David Pritchard, Christoph Kleint