Abstract: A method and an apparatus for verification of arithmetic digital circuits is disclosed, wherein a first circuit, called a specification, is compared for equivalence with a further circuit called an implementation, with equivalence occurring when and only when the specification and implementation always produce the same output signals for the same input signals. The gate level description of the specification and implementation are converted to a network of elementary arithmetic 1-bit operations (XOR, half-adders, full adders) and the equivalence of the specification and implementation is identified in that a comparison of the resultant networks from elementary arithmetic 1-bit operations is carried out directly.

Abstract: The invention relates to a method and an apparatus for verification of arithmetic digital circuits, wherein a first circuit, called a specification, is compared for equivalence with a further circuit called an implementation, with equivalence occurring when and only when the specification and implementation always produce the same output signals for the same input signals. The gate level description of the specification and implementation are converted to a network of elementary arithmetic 1-bit operations (XOR, half-adders, full adders) and the equivalence of the specification and implementation is identified in that a comparison of the resultant networks from elementary arithmetic 1-bit operations is carried out directly.