Abstract: A sensing element for an inductive position measuring device includes an excitation track, a receiving track, a substrate made of a metallic material, and a shield layer structure. The shield layer structure includes a first layer that has a dielectric property and a second layer that is electrically conductive. The shield layer structure is arranged between the substrate and the receiving track and/or between the substrate and the excitation track.

Abstract: A system and method are disclosed for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.

Abstract: A system and method are disclosed for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.

Abstract: A system and method for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.

Abstract: A system and method for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.

Abstract: A system and computer-implemented method for calculation and display of a fault propagation path. The method identifies with a computing device a fault location in an electrical circuit under test, identifies with the computing device an observation point in the electrical circuit under test, computes with the computing device a fault path from the fault location to the observation point, and displays in a waveform viewer all signals in the fault path from the fault location to the observation point in order of their creation.

Abstract: A method for formal verification of a digital circuit using a cloud-based verification engine. The method comprises extracting a proof problem from a design of a digital circuit with a local processor, reducing said proof problem to proof relevant data, encrypting said reduced proof problem, transmitting said encrypted reduced proof problem to a remote server, decrypting said encrypted reduced proof problem at said remote server, storing said reduced proof problem in a memory at said remote server, running a proof on said reduced proof problem at said remote server to generate a proof result; encrypting said proof result at said remote server; transmitting said encrypted proof result to said local processor; decrypting said encrypted proof result at said local processor; and reconstructing a verification result of said digital circuit design at said local processor using said decrypted proof result.

Abstract: A method for formal verification of a digital circuit using a cloud-based verification engine. The method comprises extracting a proof problem from a design of a digital circuit with a local processor, reducing said proof problem to proof relevant data, encrypting said reduced proof problem, transmitting said encrypted reduced proof problem to a remote server, decrypting said encrypted reduced proof problem at said remote server, storing said reduced proof problem in a memory at said remote server, running a proof on said reduced proof problem at said remote server to generate a proof result; encrypting said proof result at said remote server; transmitting said encrypted proof result to said local processor; decrypting said encrypted proof result at said local processor; and reconstructing a verification result of said digital circuit design at said local processor using said decrypted proof result.