Abstract: A multi-processor system 8 includes multiple processing devices, including DSPs (10), processor units (MPUs) (21), co-processors (30) and DMA channels (31). Some of the devices may include internal MMUs (19, 32) which allows the device (10, 21, 30, 31) to work with a large virtual address space mapped to an external shared memory (20). The MMUs (19, 32) may perform the translation between a virtual address and the physical address associated with the external shared memory (20). Access to the shared memory (20) is controlled using a unified memory management system.

Abstract: A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) defines a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line-by-line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core, hit/miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20).

Abstract: A distributed processing system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to build scenarios which meet predetermined power objectives, such as providing maximum operation within package thermal constraints or using minimum energy. Actual activities associated with the tasks are monitored during operation to ensure compatibility with the objectives. The allocation of tasks may be changed dynamically to accommodate changes in environmental conditions and changes in the task list.

Abstract: A memory traffic access controller (18) responsive to a plurality of requests to access a memory. The controller includes circuitry (18d) for associating, for each of the plurality of requests, an initial priority value corresponding to the request. The controller further includes circuitry (18b, 18d, 18e, 18f) for changing the initial priority value for selected ones of the plurality of requests to a different priority value. Lastly, the controller includes circuitry for outputting (18d) a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value.

Abstract: A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) defines a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line-by-line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core, hit/miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20).

Abstract: A cache architecture (16) for use in a processing includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) defines a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line-by-line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core, hit/miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20).

Abstract: A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) define a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line by line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core hit miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20).

Abstract: A VIVT (virtual index, virtual tag) cache (18) uses an interruptible hardware clean function to clean dirty entries in the cache during a context switch. A MAX counter (82) and a MIN register (84) define a range of cache locations which are dirty. During the hardware clean function, the MAX counter (82) counts downward while cache entries at the address given by the MAX counter (82) are written to main memory (16) if the entry is marked as dirty. If an interrupt occurs, the MAX counter is disabled until a subsequent clean request is issued after the interrupt is serviced.

Abstract: A memory traffic access controller (18) responsive to a plurality of requests to access a memory. The controller includes circuitry (18d) for associating, for each of the plurality of requests, an initial priority value corresponding to the request. The controller further includes circuitry (18b, 18d, 18e, 18f) for changing the initial priority value for selected ones of the plurality of requests to a different priority value. Lastly, the controller includes circuitry for outputting (18d) a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value.

Abstract: A DSP (10) accesses internal memory using physical addresses and has a internal MMU (19) which allows the DSP (10) to work with a large virtual address space mapped to an external memory (20). The MMU (19) performs the translation between a virtual address and the physical address associated with the external memory (20). The MMU (19) includes a translation lookaside buffer (28) and walking table logic (32) for translating virtual addresses to physical addresses.

Abstract: A memory traffic access controller (18) responsive to a plurality of requests to access a memory. The controller includes circuitry (18d) for associating, for each of the plurality of requests, an initial priority value corresponding to the request. The controller further includes circuitry (18b, 18d, 18e, 18f) for changing the initial priority value for selected ones of the plurality of requests to a different priority value. Lastly, the controller includes circuitry for outputting (18d) a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value.

Abstract: A DSP (10) accesses internal memory using physical addresses and has a internal MMU (19) which allows the DSP (10) to work with a large virtual address space mapped to an external memory (20). The MMU (19) performs the translation between a virtual address and the physical address associated with the external memory (20). The MMU (19) includes a translation lookaside buffer (28) and walking table logic (32) for translating virtual addresses to physical addresses.

Abstract: A method (50) of operating a computing system (10). The computing system comprises a cache memory (12b), and the cache memory has a predetermined number of cache lines. First, the method, for a plurality of write addresses, writes data (64) to the cache memory at a location corresponding to each of the plurality of write addresses. Second, the method cleans (70) a selected number (68) of lines in the cache memory. For each of the selected number of lines, the cleaning step evaluates a dirty indicator corresponding to data in the line and copies data from the line to another memory if the dirty indicator indicates the data in the line is dirty. Lastly, the selected number of lines which are cleaned is less than the predetermined number of cache lines.

Abstract: A memory controller circuit (18a) for coupling to a memory (24), where the memory has a plurality of rows. The memory controller circuit includes circuitry (28) for receiving signals representative of requests to access the memory. Given these signals, a first such signal representative of a first request to access the memory is received by the circuitry for receiving and comprises a first address in the memory, and a second signal representative of a second request to access the memory is received by the circuitry for receiving after the first signal and comprises a second address in the memory. The memory controller circuit also includes determining circuitry (30, RAn, AC13 Bn13 ROW, C_B_Rn) for determining whether the second address is directed to a same one of the plurality of rows as the first address. Still further, the memory controller circuit includes circuitry (30) for issuing control signals to the memory in response to receiving signals representative of requests to access the memory.