Abstract: A latch system includes a latch and a key barrel operably coupled via a clutch to the latch. The clutch has an engaged condition where operation of the key barrel unlatches the latch, and the clutch has a disengaged condition where operation of the key barrel does not unlatch the latch.

Abstract: A clutch comprises an input pinion and an output pinion associated with a rotatable locking member that has a surface inclined with respect to an axis of rotation of the locking member. The surface cooperates with an engagement member, and the locking member is movable between a first position and a second position. In the first position, the surface forms a recess to receive the engagement member, and in the second position, the surface forms a projection to force the engagement member into abutment with the input pinion to establish a driveable connection between the input pinion and the output pinion.

Abstract: A multi-processor system 8 includes multiple processing devices, including DSPs (10), processor units (MPUs) (21), co-processors (30) and DMA channels (31). Some of the devices may include internal MMUs (19, 32) which allows the device (10, 21, 30, 31) to work with a large virtual address space mapped to an external shared memory (20). The MMUs (19, 32) may perform the translation between a virtual address and the physical address associated with the external shared memory (20). Access to the shared memory (20) is controlled using a unified memory management system.

Abstract: A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) defines a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line-by-line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core, hit/miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20).

Abstract: A clutch comprises an input pinion and an output pinion associated with a rotatable locking member that has a surface inclined with respect to an axis of rotation of the locking member. The surface cooperates with an engagement member, and the locking member is movable between a first position and a second position. In the first position, the surface forms a recess to receive the engagement member, and in the second position, the surface forms a projection to force the engagement member into abutment with the input pinion to establish a driveable connection between the input pinion and the output pinion.

Abstract: A drive mechanism for a power closure latch includes a latch chassis, a power actuator fixed to the latch chassis, and a resilient member having a base at a first end and a second end that engages a drive member. The base is fixed to the latch chassis, and the drive member is driveable by the power actuator to compress the resilient member. The drive mechanism includes a toggle arm having an input and an output. The input is driveable by the drive member to toggle the output between a first position and a second position. A first end of a second arm has a pivot fixed to the latch chassis and a second end having an input for attachment to the drive member.

Abstract: The invention relates to a vehicle including a body and a tail gate mobile in rotation relative to the body between a closed position and an open position. The vehicle also includes a gas spring for actuating the tail gate, where actuation of the tail gate by the gas spring is done by a first lever arm. The vehicle includes a transmission lever for actuating the tail gate and actuation of the tail gate by the transmission lever is done by a second lever arm greater than the first lever arm. The gas spring is adapted to activate the transmission lever. The tail gate can thus be opened more easily, while limiting the bulk of the drive mechanism of the tail gate.

Abstract: A control for a window lifter of a motor vehicle includes a sensor in the form of a physical matrix having a pressure sensitive surface. The control also includes keys that define a pressure point. When pressed, the keys influence the pressure sensitive surface. The keys can be fixed to the sensor or can be connected to a support against which the sensor is fixed. The control can easily be reconfigured for different keys without modifying the sensor.

Abstract: A distributed processing system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to build scenarios which meet predetermined power objectives, such as providing maximum operation within package thermal constraints or using minimum energy. Actual activities associated with the tasks are monitored during operation to ensure compatibility with the objectives. The allocation of tasks may be changed dynamically to accommodate changes in environmental conditions and changes in the task list.

Abstract: A vehicle window lifter includes first and second parallel guide rails, a connecting arm rigidly connecting the guide rails at a point along the rails between their ends, and cable returns defining a cable path along the rails and connecting arm. The connecting arm and guide rails form a cable path for a cable, protecting the cable while providing high rigidity and simple mounting on a vehicle door.

Abstract: A modular door system provides a lower door assembly, an upper door assembly and a trim assembly. The upper door assembly is selectively removable and replaceable such that the door system is readily converted between a multiple of configurations. The trim assembly includes the interior vehicle door trim and a hinged trim portion. The hinged trim portion is defined by a trim hinge which is generally parallel to the open edge. By pivoting the hinged trim portion away from the open edge, the cavity is readily exposed for receipt of the upper door assembly. The difference in thickness of the upper door assembly is accommodated by pivoting of the hinged trim portion to permit passage of the components while still providing a seal for the cavity when the hinged trim portion is secured.

Abstract: A memory traffic access controller (18) responsive to a plurality of requests to access a memory. The controller includes circuitry (18d) for associating, for each of the plurality of requests, an initial priority value corresponding to the request. The controller further includes circuitry (18b, 18d, 18e, 18f) for changing the initial priority value for selected ones of the plurality of requests to a different priority value. Lastly, the controller includes circuitry for outputting (18d) a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value.

Abstract: A modular door system provides a lower door assembly, an upper door assembly and a trim assembly. The upper door assembly is selectively removable and replaceable such that the door system is readily converted between a multiple of configurations. The trim assembly includes the interior vehicle door trim and a hinged trim portion. The hinged trim portion is defined by a trim hinge which is generally parallel to the open edge. By pivoting the hinged trim portion away from the open edge, the cavity is readily exposed for receipt of the upper door assembly. The difference in thickness of the upper door assembly is accommodated by pivoting of the hinged trim portion to permit passage of the components while still providing a seal for the cavity when the hinged trim portion is secured.

Abstract: A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) defines a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line-by-line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core, hit/miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20).

Abstract: A cache architecture (16) for use in a processing includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) defines a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line-by-line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core, hit/miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20).

Abstract: A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) define a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line by line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core hit miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20).

Abstract: A control for a window lifter of a motor vehicle includes a sensor in the form of a physical matrix having a pressure sensitive surface. The control also includes keys that define a pressure point. When pressed, the keys influence the pressure sensitive surface. The keys can be fixed to the sensor or can be connected to a support against which the sensor is fixed. The control can easily be reconfigured for different keys without modifying the sensor.

Abstract: An object detection system for a motor vehicle comprises at least one optical sensor, a lens that directs an image of the handle and/or of a window trap area the optical sensor, and a display displaying the image of the area behind the vehicle.

Abstract: A vehicle window lifter includes first and second parallel guide rails, a connecting arm rigidly connecting the guide rails at a point along the rails between their ends, and cable returns defining a cable path along the rails and connecting arm. The connecting arm and guide rails form a cable path for a cable, protecting the cable while providing high rigidity and simple mounting on a vehicle door.

Abstract: A VIVT (virtual index, virtual tag) cache (18) uses an interruptible hardware clean function to clean dirty entries in the cache during a context switch. A MAX counter (82) and a MIN register (84) define a range of cache locations which are dirty. During the hardware clean function, the MAX counter (82) counts downward while cache entries at the address given by the MAX counter (82) are written to main memory (16) if the entry is marked as dirty. If an interrupt occurs, the MAX counter is disabled until a subsequent clean request is issued after the interrupt is serviced.