Abstract: The multiplier-adder in the Galois fields can have parameters applied to it, i.e. it is possible to choose the Galois field CG(2.sup.m) in which the polynomial operations are performed, with m at most equal to N, N being predetermined by the designer. The multiplier-adder is made up of a decoder (10) organized as N identical elementary cells receiving the generator polynomial G(m:0) and supplying the generator polynomial without its least significant bit G(m-1:0) and a polynomial marking the degree of the generator polynomial, DG(m-1:0), and a computing matrix (20) organized as N columns of identical elementary cells receiving the polynomials A, B and C of the Galois field CG(2.sup.m) and supplying a polynomial result P=(A*B).sub.modulo G +C. The multiplier-adder has usage for example as a digital signal processing processors for error detecting and correcting encoding and decoding using BCH or RS codes.

Abstract: An algebraic coder-decoder for Reed Solomon and BCH block codes is provided, namely a coprocessor of standard microprocessors specialized for algebraic processing in Galois bodies. This processor includes a clock generator which sets the rhythm of the circuit through a cycle clock and a subcycle clock, a control circuit which integrates an automatic loop system and a cycle stealing device, an arithmetic operator for carrying out simple operations on unsigned numbers representing the variables and the parameters of the algorithms a Galois operator for effecting the elementary polynomial operations in the five Galois bodies and storing the data exchanged with the host processor, an interface circuit which integrates a data exchange managament automation, a data bus, an instruction and the connections required for the control signals which connect the four blocks of the device together.

Abstract: The polynomial operator in the Galois field of the invention is organized at three levels:a multiplexer level to select and transmit the operands to be used for the successive stage of the calculation to a second level;a so-called pipeline level comprising 3 flip-flop registers to memorize the operands selected at the first level;a third level for calculation, comprising a multiplier-adder which has its inputs X, Y and Z connected to the outputs of the registers, and which gives the coefficients of the resultant polynomials in the Galois field while always performing the same calculation by repetition of the same control instruction. This operator can be applied to digital telecommunications for the encoding and decoding of BCH or RS (REED SOLOMON) error-correcting codes, and can be used to make an integrated processor capable of processing digital data in the form of octets.