Patents by Inventor Dominique Golanski
Dominique Golanski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240405146Abstract: A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.Type: ApplicationFiled: August 9, 2024Publication date: December 5, 2024Applicant: STMicroelectronics (Crolles 2) SASInventors: Antonin ZIMMER, Dominique GOLANSKI, Raul Andres BIANCHI
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Patent number: 12087873Abstract: A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.Type: GrantFiled: March 23, 2022Date of Patent: September 10, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Antonin Zimmer, Dominique Golanski, Raul Andres Bianchi
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Publication number: 20240204127Abstract: The present description concerns an avalanche photodiode comprising: a main PN junction adapted to being reverse-biased; and a plurality of semiconductor regions including at least: a first epitaxial semiconductor region of a first conductivity type; and a second semiconductor region of the second conductivity type, said second region being arranged to at least partially surround the first region, and comprising surfaces in contact with surfaces of said first region. The present description also concerns a method of manufacturing such a photodiode.Type: ApplicationFiled: December 14, 2023Publication date: June 20, 2024Applicant: STMicroelectronics International N.V.Inventors: Antonin ZIMMER, Dominique GOLANSKI, Sebastien PLACE, Guillaume MARCHAND
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INTEGRATED CIRCUIT COMPRISING A SINGLE PHOTON AVALANCHE DIODE AND CORRESPONDING MANUFACTURING METHOD
Publication number: 20240194815Abstract: A single photon avalanche diode (SPAD) includes a PN junction in a semiconductor well doped with a first type of dopant. The PN junction is formed between a first region doped with the first type of dopant and a second region doped with a second type of dopant opposite to the first type of dopant. The first doped region is shaped so as to incorporate local variations in concentration of dopants that are configured, in response to a voltage between the second doped region and the semiconductor well that is greater than or equal to a level of a breakdown voltage of the PN junction, to generate a monotonic variation in the electrostatic potential between the first doped region and the semiconductor well.Type: ApplicationFiled: February 27, 2024Publication date: June 13, 2024Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) LimitedInventors: Denis RIDEAU, Dominique GOLANSKI, Alexandre LOPEZ, Gabriel MUGNY -
Integrated circuit comprising a single photon avalanche diode and corresponding manufacturing method
Patent number: 11949035Abstract: A single photon avalanche diode (SPAD) includes a PN junction in a semiconductor well doped with a first type of dopant. The PN junction is formed between a first region doped with the first type of dopant and a second region doped with a second type of dopant opposite to the first type of dopant. The first doped region is shaped so as to incorporate local variations in concentration of dopants that are configured, in response to a voltage between the second doped region and the semiconductor well that is greater than or equal to a level of a breakdown voltage of the PN junction, to generate a monotonic variation in the electrostatic potential between the first doped region and the semiconductor well.Type: GrantFiled: December 9, 2021Date of Patent: April 2, 2024Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) LimitedInventors: Denis Rideau, Dominique Golanski, Alexandre Lopez, Gabriel Mugny -
Publication number: 20240014342Abstract: A device includes a single photon avalanche diode in a substrate and a resistor. The resistor is provided resting on an insulating trench located in a doped anode region of the single photon avalanche diode.Type: ApplicationFiled: July 10, 2023Publication date: January 11, 2024Applicants: STMicroelectronics (Research & Development) Limited, STMicroelectronics (Crolles 2) SASInventors: Sara PELLEGRINI, Dominique GOLANSKI, Alexandre LOPEZ
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Publication number: 20240014341Abstract: A device includes a single photon avalanche diode in a portion of a substrate, wherein the portion has an octagonal profile. The octagonal profile is delimited by a wall forming an octagonal contour around the portion. The device further includes an array of diodes, wherein each diode is located in a corner between four adjacent single photon avalanche diodes. Each single photon avalanche diode further includes a doped anode region. A shallow trench isolation is formed in each doped anode region. A polysilicon line forming a resistor is supported at the upper surface of the shallow trench isolation.Type: ApplicationFiled: July 10, 2023Publication date: January 11, 2024Applicants: STMicroelectronics (Research & Development) Limited, STMicroelectronics (Crolles 2) SASInventors: Isobel NICHOLSON, Sara PELLEGRINI, Dominique GOLANSKI, Alexandre LOPEZ
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Publication number: 20230178677Abstract: The present disclosure relates to a photodiode comprising a first part made of silicon and a second part made of doped germanium lying on and in contact with the first part, the first part comprising a stack of a first area and of a second area forming a p-n junction and the doping level of the germanium increasing as the distance from the p-n junction increases.Type: ApplicationFiled: December 28, 2022Publication date: June 8, 2023Applicant: STMicroelectronics (Crolles 2) SASInventors: Younes BENHAMMOU, Dominique GOLANSKI, Denis RIDEAU
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Patent number: 11581449Abstract: The present disclosure relates to a photodiode comprising a first part made of silicon and a second part made of doped germanium lying on and in contact with the first part, the first part comprising a stack of a first area and of a second area forming a p-n junction and the doping level of the germanium increasing as the distance from the p-n junction increases.Type: GrantFiled: December 4, 2019Date of Patent: February 14, 2023Assignee: STMicroelectronics (Crolles 2) SASInventors: Younes Benhammou, Dominique Golanski, Denis Rideau
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Publication number: 20220310867Abstract: A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.Type: ApplicationFiled: March 23, 2022Publication date: September 29, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Antonin ZIMMER, Dominique GOLANSKI, Raul Andres BIANCHI
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INTEGRATED CIRCUIT COMPRISING A SINGLE PHOTON AVALANCHE DIODE AND CORRESPONDING MANUFACTURING METHOD
Publication number: 20220190184Abstract: A single photon avalanche diode (SPAD) includes a PN junction in a semiconductor well doped with a first type of dopant. The PN junction is formed between a first region doped with the first type of dopant and a second region doped with a second type of dopant opposite to the first type of dopant. The first doped region is shaped so as to incorporate local variations in concentration of dopants that are configured, in response to a voltage between the second doped region and the semiconductor well that is greater than or equal to a level of a breakdown voltage of the PN junction, to generate a monotonic variation in the electrostatic potential between the first doped region and the semiconductor well.Type: ApplicationFiled: December 9, 2021Publication date: June 16, 2022Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) LimitedInventors: Denis RIDEAU, Dominique GOLANSKI, Alexandre LOPEZ, Gabriel MUGNY -
Publication number: 20200203547Abstract: The present disclosure relates to a photodiode comprising a first part made of silicon and a second part made of doped germanium lying on and in contact with the first part, the first part comprising a stack of a first area and of a second area forming a p-n junction and the doping level of the germanium increasing as the distance from the p-n junction increases.Type: ApplicationFiled: December 4, 2019Publication date: June 25, 2020Inventors: Younes BENHAMMOU, Dominique GOLANSKI, Denis RIDEAU
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Publication number: 20180374983Abstract: A method for manufacturing a SPAD photodiode starts with the delimitation of a formation area for the SPAD photodiode in a layer of semiconductor material that is doped with a first dopant type. Dopant of a second dopant type is implanted in the layer of semiconductor material to form a buried region within the formation area. An epitaxial layer is then grown on the layer of semiconductor material at least over the formation area. MOS transistors are then formed on and in the epitaxial layer at locations outside of the formation area.Type: ApplicationFiled: June 14, 2018Publication date: December 27, 2018Applicant: STMicroelectronics (Crolles 2) SASInventors: Dominique GOLANSKI, Jean JIMENEZ, Didier DUTARTRE, Olivier GONNARD
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Patent number: 9876032Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.Type: GrantFiled: October 18, 2016Date of Patent: January 23, 2018Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Sonarith Chhun, Emmanuel Josse, Gregory Bidal, Dominique Golanski, Francois Andrieu, Jerome Mazurier, Olivier Weber
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Publication number: 20170317106Abstract: An integrated circuit is formed using a substrate of a silicon-on-insulator type that includes a carrier substrate and a stack of a buried insulating layer and a semiconductor film on the carrier substrate. A first region without the stack separates a second region that includes the stack from a third region that also includes the stack. An MOS transistor has a gate dielectric region formed by a portion of the buried insulating layer in the second region and a gate region formed by a portion of the semiconductor film in the second region. The carrier substrate incorporates doped regions under the first region which form at least a part of a source region and drain region of the MOS transistor.Type: ApplicationFiled: November 28, 2016Publication date: November 2, 2017Applicants: STMicroelectronics (Rousset 2) SAS, STMicroelectronics (Crolles 2) SASInventors: Philippe Boivin, Franck Arnaud, Gregory Bidal, Dominique Golanski, Emmanuel Richard
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Patent number: 9786755Abstract: An integrated circuit includes a first zone for a first transistor and a second zone for a second transistor. The transistors are supported by a substrate of the silicon-on-insulator type that includes a semiconductor film on a buried insulating layer on a carrier substrate. In the second zone, the semiconductor film has been removed. The second transistor in the second zone includes a gate-dielectric region resting on the carrier substrate that is formed by a portion of the buried insulating layer). The first transistor in the first zone includes a gate-dielectric region formed by a dielectric layer on the semiconductor film.Type: GrantFiled: November 2, 2015Date of Patent: October 10, 2017Assignee: STMicroelectronics (Crolles 2) SASInventors: Dominique Golanski, Gregory Bidal, Simon Jeannot
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Publication number: 20170117296Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.Type: ApplicationFiled: October 18, 2016Publication date: April 27, 2017Applicants: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Sonarith Chhun, Emmanuel Josse, Gregory Bidal, Dominique Golanski, Francois Andrieu, Jerome Mazurier, Olivier Weber
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Publication number: 20160276451Abstract: An integrated circuit includes a first zone for a first transistor and a second zone for a second transistor. The transistors are supported by a substrate of the silicon-on-insulator type that includes a semiconductor film on a buried insulating layer on a carrier substrate. In the second zone, the semiconductor film has been removed. The second transistor in the second zone includes a gate-dielectric region resting on the carrier substrate that is formed by a portion of the buried insulating layer). The first transistor in the first zone includes a gate-dielectric region formed by a dielectric layer on the semiconductor film.Type: ApplicationFiled: November 2, 2015Publication date: September 22, 2016Applicant: STMicroelectronics (Crolles 2) SASInventors: Dominique Golanski, Gregory Bidal, Simon Jeannot
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Patent number: 7015105Abstract: A method of simultaneously fabricating a pair of insulated gate transistors respectively having a thin oxide and a thick oxide, and an integrated circuit including a pair of transistors of this kind. Forming low-doped NLDD areas of the thin oxide second transistor includes implanting a first dopant having a first concentration and implanting a second dopant having a second concentration lower than the first concentration. Forming low-doped areas NLDD of the first, thick oxide transistor includes only said implantation of the second dopant.Type: GrantFiled: October 26, 2001Date of Patent: March 21, 2006Assignee: STMicroelectronics, S.A.Inventors: Laurence Boissonnet, Dominique Golanski, Bruno Rauber, Andre Granier
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Publication number: 20030155618Abstract: Forming low-doped NLDD areas 17, 61 of the thin oxide second transistor T2 includes implanting a first dopant 16 having a first concentration and implanting a second dopant 22 having a second concentration lower than the first concentration. Forming low-doped areas NLDD 61 of the first, thick oxide transistor T1 includes only said implantation of the second dopant 22.Type: ApplicationFiled: June 27, 2002Publication date: August 21, 2003Inventors: Laurence Boissonnet, Dominique Golanski, Bruno Rauber, Andre Granier