Abstract: A light Emitting Diode includes a lower layer, an upper layer and between them an emissive structure suitable to emit a light radiation when an electric current passes through it. The upper layer is delimited by an upper surface, through which a portion at least of the light radiation exits. The lower layer is delimited by a lower surface for injecting electric charges. The upper surface forms a non-planar three-dimensional structure with hollow patterns and is covered by a contact structure made of one or several electrically-conductive materials, which extends against the surface, conforming to this non-planar surface.

Abstract: A method of remote data transmission over a frequency spectrum divided into a plurality of different elementary channels, between a first device and a second device, including the transmission by the first device of a first signal including a succession of first data by modulation of the first data simultaneously over a number of elementary channels of the plurality of elementary channels and the transmission of a second signal representative of a plan of use of the plurality of elementary channels including a succession of second data at least by modulation of all the second data over a single elementary channel from among said number of elementary channels.

Abstract: A method of remote data transmission over a frequency spectrum divided into a plurality of different elementary channels, between a first device and a second device, including the transmission by the first device of a first signal including a succession of first data by modulation of the first data simultaneously over a number of elementary channels of the plurality of elementary channels and the transmission of a second signal representative of a plan of use of the plurality of elementary channels including a succession of second data at least by modulation of all the second data over a single elementary channel from among said number of elementary channels.

Abstract: A processor for processing digital data includes at least one butterfly operator for execution of a fast Fourier transform computation, the butterfly operator having a pipeline architecture for synchronized receiving and processing of input data according to a clock signal. This pipeline architecture includes a plurality of elements including addition, subtraction, and multiplication hardware modules and links for synchronized transmission of data between the modules. At least one element of this pipeline architecture is configurable by at least one programmable parameter, between a first configuration wherein the butterfly operator performs the fast Fourier transform computation and a second configuration wherein the butterfly operator performs a metric computation of an implementation of a channel decoding algorithm.

Abstract: An addition/subtraction hardware operator includes a plurality of addition/subtraction hardware modules and a plurality of transmission links between these modules, on one hand, and between inputs and outputs of the operator and these modules, on the other hand, according to a pre-determined structure for performing arithmetical calculations. At least a part of the addition/subtraction hardware modules and at least a part of the links between these modules can be configured by at least one programmable parameter, at least between a first configuration in which the operator finalizes a computation of real parts of fast Fourier transform coefficients, a second configuration in which the operator finalizes a computation of imaginary parts of fast Fourier transform coefficients, and a third configuration in which the operator carries out a computation of path metrics and survivors values of a Viterbi algorithm implementation.

Abstract: A method of identifying an RF signal for a cognitive radio system. The signal is identified with a digital watermarking performed downstream from the digital modulation of the symbols to be transmitted. A method of detecting an RF signal watermarked is also disclosed. The identification method includes demodulating the received RF signal as a baseband, converting it digitally, and correlating the digital signal obtained with a predetermined digital signature. The correlation values are averaged using a recursive filter and the maximum value of the average values output from the filter is compared to a threshold to decide whether the RF signal is present.

Abstract: A processor for processing digital data includes at least one butterfly operator for executing an FFT/IFFT computation. This butterfly operator contains a first stage of complex multiplication and a second stage of complex addition and subtraction. Each of these two stages contains a plurality of addition/subtraction hardware modules and data transmission links between these modules. At least a part of the addition/subtraction modules of each stage of the butterfly operator and at least a part of the links between these modules are configurable with the aid of at least one programmable parameter, between a first configuration in which the butterfly operator carries out said fast Fourier transform computation and a second configuration in which the butterfly operator carries out a computation of branch metrics values and of path metrics and survivors values of a Viterbi algorithm.

Abstract: A method of identifying an RF signal for a cognitive radio system. The signal is identified with a digital watermarking performed downstream from the digital modulation of the symbols to be transmitted. A method of detecting an RF signal watermarked is also disclosed. The identification method includes demodulating the received RF signal as a baseband, converting it digitally, and correlating the digital signal obtained with a predetermined digital signature. The correlation values are averaged using a recursive filter and the maximum value of the average values output from the filter is compared to a threshold to decide whether the RF signal is present.

Abstract: A processor for processing digital data includes at least one butterfly operator for execution of a fast Fourier transform computation, the butterfly operator having a pipeline architecture for synchronized receiving and processing of input data according to a clock signal. This pipeline architecture includes a plurality of elements including addition, subtraction, and multiplication hardware modules and links for synchronized transmission of data between the modules. At least one element of this pipeline architecture is configurable by at least one programmable parameter, between a first configuration wherein the butterfly operator performs the fast Fourier transform computation and a second configuration wherein the butterfly operator performs a metric computation of an implementation of a channel decoding algorithm.

Abstract: A processor for processing digital data includes at least one butterfly operator for executing an FFT/IFFT computation. This butterfly operator contains a first stage of complex multiplication and a second stage of complex addition and subtraction. Each of these two stages contains a plurality of addition/subtraction hardware modules and data transmission links between these modules. At least a part of the addition/subtraction modules of each stage of the butterfly operator and at least a part of the links between these modules are configurable with the aid of at least one programmable parameter, between a first configuration in which the butterfly operator carries out said fast Fourier transform computation and a second configuration in which the butterfly operator carries out a computation of branch metrics values and of path metrics and survivors values of a Viterbi algorithm.

Abstract: An addition/subtraction hardware operator includes a plurality of addition/subtraction hardware modules and a plurality of transmission links between these modules, on one hand, and between inputs and outputs of the operator and these modules, on the other hand, according to a pre-determined structure for performing arithmetical calculations. At least a part of the addition/subtraction hardware modules and at least a part of the links between these modules can be configured by at least one programmable parameter, at least between a first configuration in which the operator finalizes a computation of real parts of fast Fourier transform coefficients, a second configuration in which the operator finalizes a computation of imaginary parts of fast Fourier transform coefficients, and a third configuration in which the operator carries out a computation of path metrics and survivors values of a Viterbi algorithm implementation.

Abstract: Disclosed is a data transmission process using repetitive sets of spreading sequences, and corresponding transmitted and receiver. According to the invention, spectrum spreading is done on symbol packets using set of pseudo-random sequences used repetitively. This thus reduces interference between symbols. The present invention is applicable to digital communications by spectrum spreading.

Abstract: Embodiments for non-coherent phase differential and multiple orthogonal signal modulation/demodulation are disclosed. One illustrative embodiment may include: a method for non-coherent reception of a signal with spectrum spreading, comprising performing a multiple orthogonal signal demodulation operation on the signal; performing a phase differential demodulation operation on the signal; and combining the results of the multiple orthogonal signal demodulation operation on the signal and the phase differential demodulation operation on the signal.

Abstract: A generator of repetitive sets of spreading sequences includes an element for counting and for forming an address and a table containing L sets of S sequences. The address contains q+log2S bits. The q bits are used for selecting one set among L (L=2q) sets. The log2S bits are used for selecting one sequence among the S sequences in the set.

Abstract: At transmission, the data to be transmitted is divided into N data blocks, these N blocks are processed in parallel in N M-ary orthogonal keying (MOK) modulation channels, each modulation using a group of spread codes, each channel emitting a signal. All of these signals are transmitted in series. At reception, the signal received is processed in N M-ary orthogonal keying (MOK) demodulation channels, and the blocks obtained are grouped together in series.

Abstract: The invention relates to a method and device for the joint detection of data transmitted by direct sequence spread spectrum (DSSS). The device comprises means of using a Cholesky decomposition to calculate a matrix U such that: L=UH×U, where L is an equalization matrix and U is an upper triangular matrix. The means for using a Cholesky decomposition comprise MAC cells (MAC1, MAC2, . . . , MACN) and a diagonal cell (DIAG) of a systolic network. The MAC cells and the diagonal cell are also used to calculate an estimated vector {circumflex over (d)} of received data. For example, the invention applies to the field of digital mobile phone transmissions.

Abstract: A method and an apparatus for transmitting data using multi-MOK modulation/demodulation transmission process corresponding to transmitter and receiver are disclosed. At transmission, the data to be transmitted is divided into N data blocks. The N blocks are processed in parallel in N M-ary orthogonal keying (MOK) modulation channels, each modulation using a group of spread codes, each channel emitting a signal, all these signals (S) are transmitted in series. At reception, the signal received (R) is processed in N MOK demodulation channels and the blocks obtained are grouped together in series.

Abstract: At transmission, the data to be transmitted is divided into N data blocks, these N blocks are processed in parallel in N M-ary orthogonal keying (MOK) modulation channels, each modulation using a group of spread codes, each channel emitting a signal, all these signals (S) are transmitted in series. At reception, the signal received (R) is processed in N M-ary orthogonal keying (MOK) demodulation channels and the blocks obtained are grouped together in series.

Abstract: A generator of repetitive sets of spreading sequences comprising means (20) for counting and for forming an address and a table (30) containing L sets of S sequences, wherein the address contains q+log2S bits, wherein the q bits are used for selecting one set among L (L=2q) sets and wherein the log2S bits are used for selecting one sequence among the S sequences in the set.

Abstract: Receiver module and receiver formed from several cascaded module. The module comprises inputs (E1, E2, E3, E4) and outputs (S1, S2, S3, S4) connected to a selection means (44) circuit, to a switching means (45) circuit, and to a decoding means (46, 58, 60) circuit. Such modules can be cascaded by simply connecting the corresponding inputs and outputs. The final module delivers the transmitted information. Application to differential phase modulation and orthogonal modulation spread spectrum digital transmission.