Abstract: In one embodiment, a power supply controller is configured to operate a plurality of switches in a buck-boost mode to control an output voltage wherein at least one switch of the plurality of switches is enabled for a substantially fixed portion of a cycle of the buck-boost mode.

Abstract: In one embodiment, a power supply controller is configured to operate a plurality of switches in a buck-boost mode to control an output voltage wherein at least one switch of the plurality of switches is enabled for a substantially fixed portion of a cycle of the buck-boost mode.

Abstract: A smart card reader (8) includes a detection circuit (26) that has a plurality of inputs (30, 38, 42) for monitoring a plurality of operating conditions of the smart card reader. A plurality of outputs (53-56) provide a plurality of sense signals (VCCOK, VCCOC, VBATOK, CRDINS). A multiplexer (60) has a plurality of sense inputs coupled to the plurality of outputs of the detection circuit. A selection input (67, 68) receives a selection signal (ADDR) for routing one of the plurality of sense signals to an output (32) as a status signal (STATUS).

Abstract: An integrated smart card reader circuit (10) includes a first signal path (64, 65) that is enabled by a first value of programming data (POL) for routing a card insertion signal (CRDDET) from a first lead (42) to a second lead (32) of the card reader circuit as a detection signal (INT). A second signal path (66, 67) operates in response to a second value of the programming data, and is coupled to the first lead for inverting the card insertion signal to produce the detection signal at the second lead. The programming data is indicative of the polarity of the card insertion signal, which depends on the type of detection switch (17) used to determine when a smart card (15) is inserted in a card reader (8).

Abstract: A smart card reader (8) includes a detection circuit (26) that has a plurality of inputs (30, 38, 42) for monitoring a plurality of operating conditions of the smart card reader. A plurality of outputs (53-56) provide a plurality of sense signals (VCCOK, VCCOC, VBATOK, CRDINS). A multiplexer (60) has a plurality of sense inputs coupled to the plurality of outputs of the detection circuit. A selection input (67, 68) receives a selection signal (ADDR) for routing one of the plurality of sense signals to an output (32) as a status signal (STATUS).

Abstract: An integrated switching mode power supply (10) has a follower device (59) providing a supply voltage (VBOOT) to a node (70) of the power supply. A driver circuit operates in response to an input signal (VCONTROL) and has an output (40) for providing a drive signal (VDRIVE) that bootstraps the node to a potential greater than the supply voltage.

Abstract: An integrated switching mode power supply (10) has a follower device (59) providing a supply voltage (VBOOT) to a node (70) of the power supply. A driver circuit operates in response to an input signal (VCONTROL) and has an output (40) for providing a drive signal (VDRIVE) that bootstraps the node to a potential greater than the supply voltage.

Abstract: A power supply (100) uses two comparators (C1, C2) to clamp the peak primary side current of the power supply. A reference voltage (Vref) is provided as an input to a first comparator (C2) and is used to clamp the primary current to a minimum level. A feedback voltage (VFB) from the secondary side of the power supply is used to clamp the primary current to a maximum level. In one approach, the outputs of the two comparators are combined using a logic gate (A1) and a feedback voltage (Vsense) from the primary side is provided as an input to each of the two comparators.

Abstract: A charge pump apparatus and a method for operating a charge pump power supply having an input and an output, the output coupled to a load, and the load having a bulk capacitor coupled thereto for providing a voltage source for the load. A source of varying voltage is provided as an input to the charge pump power supply. The output of the charge pump power supply is coupled to the load and to the bulk capacitor, and the charge pump power supply is operated in a first mode to provide current for charging the bulk capacitor when the voltage at the load is below a predetermined voltage, and alternatively in a second mode to cease the supply of current to the bulk capacitor when the voltage at the power supply is above a predetermined voltage. The charge pump comprises a capacitor-diode arrangement with a transistor switch operable to control the current flow through the charge pump and to the bulk capacitor.

Abstract: A charge pump apparatus and a method for operating a charge pump power supply having an input and an output, the output coupled to a load, and the load having a bulk capacitor coupled thereto for providing a voltage source for the load. A source of varying voltage is provided as an input to the charge pump power supply. The output of the charge pump power supply is coupled to the load and to the bulk capacitor, and the charge pump power supply is operated in a first mode to provide current for charging the bulk capacitor when the voltage at the load is below a predetermined voltage, and alternatively in a second mode to cease the supply of current to the bulk capacitor when the voltage at the power supply is above a predetermined voltage. The charge pump comprises a capacitor-diode arrangement with a transistor switch operable to control the current flow through the charge pump and to the bulk capacitor.

Abstract: A cache memory architecture having a separate redundant read bus fully dedicated to redundancy and fed by a single spare sub-array common to all memory sub-arrays of the cache memory. Redundant sense amplifiers are dotted to the redundant read bus, and normal sense amplifiers are connected to a main read bus. Normal and redundant data are valid and available at the same time at the outputs of the normal and redundant sense amplifiers. When the late select address signals become valid, then the correct information can be selected via a multiplexer provided with an INHIBIT input. The multiplexer is normally controlled by decoded signals generated by a decoder, unless redundancy is required. If redundancy is required, the information generated by the bit address comparator forces the multiplexer, via the INHIBIT input, to select the redundant read bus, instead of one read bus of the main read bus, and to output the redundant byte as the selected one.

Abstract: There is described a double stage sense amplifier (4) in bipolar technology achieving very high speed operation without saturation or connection problems. For each memory cell column of the computer member system (1), a first stage or column sense stage (4.1) amplifies the differential input signal (V) produced on the pair of bit lines (BLL, BLR) according to the information read from one CMOS memory cell of the memory cell array (3.1) to provide a first differential output signal (V1) available at output terminals (10.1, 10.2). The output terminals of all the first stage (4.1 to 4.n) are connected to a first-data out bus comprised of the data lines (DLC1, DLT1). A second stage or final stage (4') amplifies the first differential output signal developed on the data lines to provide a second differential output signal (V2) at output terminals (17.1, 17.2). The second stage of the common base amplifier type is comprised of two transistors (T9, T10).

Abstract: The present invention relates to fast complementary emitter follower drivers/buffers to be used in either a CMOS or pure complementary bipolar environment. The output driver (22) comprises top NPN and bottom PNP output transistors (T1, T2) with a common output node (N) connected therebetween. A terminal (15) is connected to the said output node (N) where the output signal (VOUT) is available. The pair of bipolar output transistors is biased between the first and second supply voltages (VH, GND). The output driver is provided with a voltage translator circuit (S) connected between the base nodes (B1, B2) of the output transistors (T1, T2). Logic signals (IN1, IN2), supplied by a preceding driving circuit (21), are applied to said base nodes. According to the invention, the voltage translator circuit (S) comprises two diodes (D1, D2) connected in series, preferably implemented with a main bipolar transistor having a junction shorted by a diode connected transistor to form a Darlington-like configuration.

Abstract: A two stage address decoder circuit (AD) for 1/64 decode operation is disclosed which operates at high speed with low power consumption. Briefly stated, the circuit includes a first stage comprised of two predecoder circuits operable to develop predecoded output signals in response to input address signals and corresponding inverted address signals. Each predecoder circuit consists of a lower power high speed Differential Cascode Current Switch tree with its associated current source. The second or final decode stage is comprised of a plurality of final decoding circuits. Each final circuit consisting of a 2 way OR gate dynamically activated through a switched current source. The inputs of the 2 way OR gate are connected to one pair of the predecoded output signals. Final decoder circuits provide final decoded output signals which drive the word lines of a memory cell array.

Abstract: Memory comprising a matrix of conventional Harper pnp cells and peripheral circuits which allows it to be used either as a random access memory or as an associative memory. In addition to the read/write circuits which are inhibited in search mode, it comprises search mode control circuits 7-1 to 7-m to provide the memory cells with a search argument DI-1 to DI-m and search circuits 11-1 to 11-n connected to the word lines for detecting the match or mismatch conditions. A search restore circuit 15 common to all word lines WL is used to restore the work lines to a quiescent voltage once the search operation is completed. Circuits 7 and 11 are inhibited in read/write mode.