Patents by Inventor Dominique Tournier
Dominique Tournier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200373754Abstract: The present invention relates to a device for protecting electrical equipment (23), comprising: a first branch (21) for limiting current including a current source; a second conduction branch (22) mounted parallel to the limitation branch (21), the impedance of the conduction branch (22) being less than or equal to 10% of the impedance of the limitation branch (21); a control unit (3) for switching the operating mode of the device between: a first operating mode, in which the electric current circulates through the limitation branch (21) without circulating in the conduction branch (22); and a second operating mode, in which the electric current circulates through the limitation and conduction branches (21, 22).Type: ApplicationFiled: January 11, 2018Publication date: November 26, 2020Inventors: Dominique TOURNIER, Maxime BERTHOU, Gonzalo PICUN
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Patent number: 9450396Abstract: The invention pertains to a DC current interruption system able to open a DC line with inductive behavior, comprising a primary mechanical breaker (S0), a secondary mechanical breaker (S1) and an electronic overvoltage protection circuit (B1, B2) comprising at least one transistor. The DC current interruption system of the invention furthermore comprises an electronic opening system (72, 76) comprising a passive circuit able to auto-bias the electronic protection circuit (B1, B2) upon the opening of said primary mechanical breaker (S0), so as to trigger a switching of said at least one transistor (M1, M2, IG1) making it possible to limit the voltage and the current in the DC line, total interruption of said DC line being obtained by subsequent opening of said secondary mechanical breaker (S1).Type: GrantFiled: July 2, 2012Date of Patent: September 20, 2016Assignee: MERSEN FRANCE SB SASInventors: Franck Sarrus, Florent Balboni, Dominique Tournier
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Patent number: 9356113Abstract: The invention concerns a method for producing a field effect transistor having a trench gate comprising: —the forming (110) of at least one trench (11, 12, 13) in a semi-conductive substrate (1) having a first type of conductivity, said substrate comprising two opposing faces called front face and rear face, —the primary implantation (120) of ions having a second type of conductivity so as to implant each trench of the substrate to form an active gate area, —the depositing (160) of a layer of polycrystalline silicon having the second type of conductivity on the implanted active gate area, —the oxidation (160) of the layer of polycrystalline silicon, and —the metallization (180) of the substrate on the front and rear faces of same in order to form active source and drain areas.Type: GrantFiled: September 5, 2012Date of Patent: May 31, 2016Assignees: Institut National des Sciences Appliquees de Lyon, Université Claude Bernard Lyon 1, Centre National de la Recherche Scientifique (CNRS), Ecole Centrale De Lyon, Consejo Superior De Investigaciones Cienti{acute over (f)}icas (CSIC)Inventors: Dominique Tournier, Florian Chevalier, Philippe Godignon, José Millan
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Publication number: 20150349084Abstract: The invention concerns a method for producing a field effect transistor having a trench gate comprising:—the forming (110) of at least one trench (11, 12, 13) in a semi-conductive substrate (1) having a first type of conductivity, said substrate comprising two opposing faces called front face and rear face,—the primary implantation (120) of ions having a second type of conducitivity so as to implant each trench of the substrate to form an active gate area,—the depositing (160) of a layer of polycrystalline silicon having the second type of conductivity on the implanted active gate area,—the oxidation (160) of the layer of polycrystalline silicon, and—the metallisation (180) of the substrate on the front and rear faces of same in order to form active source and drain areas.Type: ApplicationFiled: September 5, 2012Publication date: December 3, 2015Applicants: Institut National des Sciences Appliquees de Lyon, Université Claude Bernard Lyon 1, Centre National de la Recherche Scientifique (CNRS, Ecole Centrale De Lyon, Consejo Superior De Investigaciones Cientificas (CSIC)Inventors: Dominique TOURNIER, Florian CHEVALIER, Philippe GODIGNON, José MILLAN
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Publication number: 20150207314Abstract: The device for protecting a circuit includes a nonlinear resistance and a Zener diode. The nonlinear resistance is designed to be connected to the terminals of a power supply source of the circuit. The Zener diode and the nonlinear resistance each includes a first connecting end and a second connecting end. The first end of the Zener diode is connected to the second end of the nonlinear resistance. The device further includes a current limiter component, able to limit the intensity of the current passing through it. The current limiter component is connected between the second end of the nonlinear resistance and the second end of the Zener diode.Type: ApplicationFiled: January 8, 2015Publication date: July 23, 2015Inventors: Dominique TOURNIER, Gianfranco DE PALMA
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Patent number: 9030796Abstract: A system for supplying direct current and DC voltage is provided. The system comprise a first supply branch having a first DC voltage source and a power field-effect transistor of a current limiter which are connected in series, and a second supply branch having a second DC voltage source. The power transistor has a current/voltage characteristic with a first inverse polarization area without current limitation, and a second conduction area with current limitation based on a current threshold. The power field-effect transistor is connected to the first voltage source with an inverse polarization when the voltage source of the first branch is operating normally.Type: GrantFiled: December 1, 2011Date of Patent: May 12, 2015Assignee: MERSEN France SB SASInventors: Franck Sarrus, Thierry Rambaud, Dominique Tournier, Philippe Godignon, Jean-François De Palma
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Patent number: 9018685Abstract: The invention relates to a structure comprising an n-type substrate (1) having a bottom surface (10) and a top surface (11), a drain (D) contacting the bottom surface (10) of the substrate (1), a first n-type semiconductor region (2) having a top surface (21) provided with a contact area (210), a source (S) contacting the contact area (210), and a second p-type semiconductor region (3) arranged inside the first semiconductor region (2) and defining first and second conduction channels (C1, C2) between the drain and the source, characterized in that said structure comprises first and second metal gratings (G1, G2), each of which has a portion (40, 71) contacting the first semiconductor region (2) so as to form a Schottky junction.Type: GrantFiled: July 13, 2011Date of Patent: April 28, 2015Assignees: Institut National des Sciences Appliquees de Lyon, Centre National de la Recherche ScientifiqueInventors: Dominique Tournier, Pierre Brosselard, Florian Chevalier
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Publication number: 20140126098Abstract: The invention pertains to a DC current interruption system able to open a DC line with inductive behaviour, comprising a primary mechanical breaker (S0), a secondary mechanical breaker (S1) and an electronic overvoltage protection circuit (B1, B2) comprising at least one transistor. The DC current interruption system of the invention furthermore comprises an electronic opening system (72, 76) comprising a passive circuit able to auto-bias the electronic protection circuit (B1, B2) upon the opening of said primary mechanical breaker (S0), so as to trigger a switching of said at least one transistor (M1, M2, IG1) making it possible to limit the voltage and the current in the DC line, total interruption of said DC line being obtained by subsequent opening of said secondary mechanical breaker (S1).Type: ApplicationFiled: July 2, 2012Publication date: May 8, 2014Applicant: MERSEN FRANCE SB SASInventors: Franck Sarrus, Florent Balboni, Dominique Tournier
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Publication number: 20140063672Abstract: A system for supplying direct current and DC voltage is provided. The system comprise a first supply branch having a first DC voltage source and a power field-effect transistor of a current limiter which are connected in series, and a second supply branch having a second DC voltage source. The power transistor has a current/voltage characteristic with a first inverse polarization area without current limitation, and a second conduction area with current limitation based on a current threshold. The power field-effect transistor is connected to the first voltage source with an inverse polarization when the voltage source of the first branch is operating normally.Type: ApplicationFiled: December 1, 2011Publication date: March 6, 2014Applicant: MERSEN FRANCE SB SASInventors: Franck Sarrus, Thierry Rambaud, Dominique Tournier, Philippe Godignon, Jean-François De Palma
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Publication number: 20130250467Abstract: The invention relates to a power transistor for protecting, by limiting current, an electrical power supply, including one or more basic power vertical-junction field-effect transistors (602). Each basic power vertical junction field-effect transistor (602) includes at least one semiconductor depletion region (618, 620) forming a partially buried gate that defines a vertical channel (622) inside a first region (612). Each basic transistor includes a semiconductor depletion region (618, 620) forming an upper surface gate that is not buried, and defining a side channel inside a region (612) vertically adjacent to the first region.Type: ApplicationFiled: December 1, 2011Publication date: September 26, 2013Applicant: MERSEN FRANCE SB SASInventors: Franck Sarrus, Thierry Rambaud, Dominique Tournier, Philippe Godignon, Jean-Francois De Palma
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Publication number: 20130119443Abstract: The invention relates to a structure comprising an n-type substrate (1) having a bottom surface (10) and a top surface (11), a drain (D) contacting the bottom surface (10) of the substrate (1), a first n-type semiconductor region (2) having a top surface (21) provided with a contact area (210), a source (S) contacting the contact area (210), and a second p-type semiconductor region (3) arranged inside the first semiconductor region (2) and defining first and second conduction channels (C1, C2) between the drain and the source, characterized in that said structure comprises first and second metal gratings (G1, G2), each of which has a portion (40, 71) contacting the first semiconductor region (2) so as to form a Schottky junction.Type: ApplicationFiled: July 13, 2011Publication date: May 16, 2013Applicants: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, INSTITUT NATIONAL DES SCIENCES APPLIQUEES DE LYONInventors: Dominique Tournier, Pierre Brosselard, Florian Chevalier