Abstract: A glazing, at least partially transparent, the main surface of which is divided into partial surfaces capable of being concealed, opacified, colored and/or illuminated independently of each other, in whole, in part and/or in accordance with designs, the partial surfaces being associated with invisible touch controls identified by prints, an identification design on the one hand, an offset design for identification and tracking of invisible offset touch controls on the other hand, being associated with at least one of the partial surfaces.

Abstract: A method of manufacturing an interposer product that includes: forming on a same side of an interposer substrate, by a common process, first and second portions of a gold layer, wherein the first portion of the gold layer constitutes a wire-bonding pad; depositing a Au—Sn solder on the second portion of the gold layer, the Au—Sn solder comprising a gold-tin alloy having a first composition; merging the deposited Au—Sn solder with the second portion of the gold layer by performing a reflow process to form at least one bonding bump, wherein a majority of the bonding bump is made of a eutectic composition of the gold-tin alloy, and wherein the first composition has a smaller proportion of gold than is in the eutectic composition of the gold-tin alloy; and planarizing the bonding bump to form a flat bonding bump having a selected height.

Abstract: The present invention relates to a method and system for testing integrity of a passivation layer (108) covering a semiconductor device. A structured layer of electrically conducting material (104) is deposited onto at least a portion of a top surface of a substrate (102) of the semiconductor device. The structured layer (104) comprises a plurality of bands (104.1, 104.2) connected to at least two contacts (106.1, 106.2) and disposed on the at least a portion of the top surface such that one of consecutive bands (104.1, 104.2) and consecutive portions of the bands (104.1, 104.2) are connected to different contacts (106.1, 106.2). A passivation layer (108) is deposited onto the at least a portion of the top surface of the substrate (102) and the structured layer (104) such that material of the passivation layer(108) is disposed between the bands of conducting material (104.1, 104.2) and on top of the structured layer (104).

Abstract: The present invention relates to a method and system for testing integrity of a passivation layer (108) covering a semiconductor device. A structured layer of electrically conducting material (104) is deposited onto at least a portion of a top surface of a substrate (102) of the semiconductor device. The structured layer (104) comprises a plurality of bands (104.1, 104.2) connected to at least two contacts (106.1, 106.2) and disposed on the at least a portion of the top surface such that one of consecutive bands (104.1, 104.2) and consecutive portions of the bands (104.1, 104.2) are connected to different contacts (106.1, 106.2). A passivation layer (108) is deposited onto the at least a portion of the top surface of the substrate (102) and the structured layer (104) such that material of the passivation layer(108) is disposed between the bands of conducting material (104.1, 104.2) and on top of the structured layer (104).

Abstract: The present invention provides a method for making a vertical interconnect through a substrate. The method makes use of a sacrificial buried layer 220 arranged in between the first side 202 and the second side 204 of a substrate 200. After having etched trenches 206 and 206? from the first side, the sacrificial buried layer 220 functions as a stop layer during etching of holes 218 and 218? from the second side, therewith protecting the trenches from damage during overetch of the holes. The etching of trenches is completely decoupled from etching of the holes providing several advantages for process choice and device manufacture. After removing part of the sacrificial buried layer to interconnect the trenches and the holes, the resulting vertical interconnect hole is filled to form a vertical interconnect.

Abstract: The present invention provides a method for making a vertical interconnect through a substrate. The method makes use of a sacrificial buried layer 220 arranged in between the first side 202 and the second side 204 of a substrate 200. After having etched trenches 206 and 206? from the first side, the sacrificial buried layer 220 functions as a stop layer during etching of holes 218 and 218? from the second side, therewith protecting the trenches from damage during overetch of the holes. The etching of trenches is completely decoupled from etching of the holes providing several advantages for process choice and device manufacture. After removing part of the sacrificial buried layer to interconnect the trenches and the holes, the resulting vertical interconnect hole is filled to form a vertical interconnect.