Patents by Inventor Don Agneta
Don Agneta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7263570Abstract: A method of electrically coupling a central processing unit (CPU) of a network server to a plurality of network interface modules. The method comprises providing each of the plurality of network interface modules with a respective bus adapter chip to route an I/O bus having a first format from the central processing unit to a primary side of each of the plurality of bus adaptor chips and routing another I/O bus of the first format from a secondary side of each of the plurality of bus adapter chips to respective ones of the network interface modules. The bus adapter chips also provide for arbitered access along the I/O buses and isolation of the CPU from electrical disruption when one the network interface modules is removed.Type: GrantFiled: May 3, 2006Date of Patent: August 28, 2007Assignee: Micron Technology, Inc.Inventors: Stephen E. J. Papa, Carlton G. Amdahl, Michael G. Henderson, Don Agneta, Don Schiro, Dennis H. Smith
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Publication number: 20060206649Abstract: A method of electrically coupling a central processing unit (CPU) of a network server to a plurality of network interface modules. The method comprises providing each of the plurality of network interface modules with a respective bus adapter chip to route an I/O bus having a first format from the central processing unit to a primary side of each of the plurality of bus adaptor chips and routing another I/O bus of the first format from a secondary side of each of the plurality of bus adapter chips to respective ones of the network interface modules. The bus adapter chips also provide for arbitered access along the I/O buses and isolation of the CPU from electrical disruption when one the network interface modules is removed.Type: ApplicationFiled: May 3, 2006Publication date: September 14, 2006Inventors: Stephen Papa, Carlton Amdahl, Michael Henderson, Don Agneta, Don Schiro, Dennis Smith
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Patent number: 7065600Abstract: A method of electrically coupling a central processing unit (CPU) of a network server to a plurality of network interface modules. The method comprises providing each of the plurality of network interface modules with a respective bus adapter chip to route an I/O bus having a first format from the central processing unit to a primary side of each of the plurality of bus adaptor chips and routing another I/O bus of the first format from a secondary side of each of the plurality of bus adapter chips to respective ones of the network interface modules. The bus adapter chips also provide for arbitered access along the I/O buses and isolation of the CPU from electrical disruption when one the network interface modules is removed.Type: GrantFiled: March 23, 2004Date of Patent: June 20, 2006Assignee: Micron Technology, Inc.Inventors: Stephen E. J. Papa, Carlton G. Amdahl, Michael G. Henderson, Don Agneta, Don Schiro, Dennis H. Smith
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Publication number: 20040210701Abstract: A method of electrically coupling a central processing unit (CPU) of a network server to a plurality of network interface modules. The method comprises providing each of the plurality of network interface modules with a respective bus adapter chip to route an I/O bus having a first format from the central processing unit to a primary side of each of the plurality of bus adaptor chips and routing another I/O bus of the first format from a secondary side of each of the plurality of bus adapter chips to respective ones of the network interface modules. The bus adapter chips also provide for arbitered access along the I/O buses and isolation of the CPU from electrical disruption when one the network interface modules is removed.Type: ApplicationFiled: March 23, 2004Publication date: October 21, 2004Inventors: Stephen E.J. Papa, Carlton G. Amdahl, Michael G. Henderson, Don Agneta, Don Schiro, Dennis H. Smith
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Patent number: 6742069Abstract: A method of electrically coupling a central processing unit (CPU) of a network server to a plurality of network interface modules. The method comprises providing each of the plurality of network interface modules with a respective bus adapter chip to route an I/O bus having a first format from the central processing unit to a primary side of each of the plurality of bus adapter chips and routing another I/O bus of the first format from a secondary side of each of the plurality of bus adapter chips to respective ones of the network interface modules. The bus adapter chips also provide for arbitered access along the I/O buses and isolation of the CPU from electrical disruption when one of the network interface modules is removed.Type: GrantFiled: October 30, 2001Date of Patent: May 25, 2004Assignee: Micron Technology, Inc.Inventors: Stephen E. J. Papa, Carlton G. Amdahl, Michael G. Henderson, Don Agneta, Don Schiro, Dennis H. Smith
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Publication number: 20030009613Abstract: A method of electrically coupling a central processing unit of a network server to a plurality of network interface modules. The method comprises routing an I/O bus having a first format from said central processing unit to primary sides of a plurality of bus adaptor chips. The method further comprises routing an I/O bus of said first format from a secondary side of said bus adaptor chips to respective ones of said network interface modules.Type: ApplicationFiled: October 30, 2001Publication date: January 9, 2003Inventors: Stephen E. J. Papa, Carlton G. Amdahl, Michael G. Henderson, Don Agneta, Don Schiro, Dennis H. Smith
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Patent number: 6324608Abstract: Methods of removing and replacing data processing circuitry are provided comprising removing a network interface module from the computer without powering down the computer and removing an interface card from the network interface module. The further acts of replacing the interface card into the network interface module and replacing the network interface module into the computer without powering down the network computer are also performed in accordance with this method.Type: GrantFiled: October 1, 1997Date of Patent: November 27, 2001Assignee: Micron ElectronicsInventors: Stephen E. J. Papa, Carlton G. Amdahl, Michael G. Henderson, Don Agneta, Don Schiro, Dennis H. Smith
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Patent number: 6253334Abstract: A fault-tolerant computer system includes a processor and a memory, connected to a system bus. The system includes at least two mirrored circuits, at least two mirrored IO devices, a detection means and a re-route means. The two mirrored circuits each include an interface to the system bus, and an IO interface. The input/output interface of each of the mirrored circuits is connected to one of the two mirrored IO devices. Detection means detect a load imbalance in the data transfer between the system bus and either one of the two mirrored IO devices. In response to the detection of a load imbalance, the re-route means re-routes the data transfer between the system bus and the other one of the two mirrored IO devices. In another embodiment, a fault-tolerant computer system includes a first, second and third IO bus, legacy devices, and two IO devices. The first IO bus is connected to the system bus. The legacy devices are connected to the first IO bus.Type: GrantFiled: October 1, 1997Date of Patent: June 26, 2001Assignee: Micron Electronics, Inc.Inventors: Carlton G. Amdahl, Dennis H. Smith, Don A. Agneta
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Patent number: 6249834Abstract: A system for expanding the loading capacity of a PCI bus in an information processing system having a multiple bus architecture. In one embodiment, the system comprises a processor-to-PCI bridge connected to a plurality of PCI-to-PCI bridges to generate multiple PCI buses. A plurality of add-in board connectors are coupled to each of the generated PCI buses. In another embodiment, the system comprises two or more processor-to-PCI bridges connected to a plurality of PCI-to-PCI bridges to generate multiple PCI buses. The resulting system expands the loading capacity of a PCI bus while adding resistance to single point failures.Type: GrantFiled: October 1, 1997Date of Patent: June 19, 2001Assignee: Micron Technology, Inc.Inventors: Michael G. Henderson, Carlton G. Amdahl, Dennis H. Smith, Don Agneta
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Patent number: 6195717Abstract: A method for expanding the loading capacity of a PCI bus in an information processing system having a multiple bus architecture. In one embodiment, the method comprises connecting a processor-to-PCI bridge to a plurality of PCI-to-PCI bridges to generate multiple PCI buses. A plurality of add-in board connectors are coupled to each of the generated PCI buses. In another embodiment, the method comprises connecting two or more processor-to-PCI bridges to a plurality of PCI-to-PCI bridges to generate multiple PCI buses. The resulting system expands the loading capacity of a PCI bus while adding fault-tolerance and resistance to single point failures.Type: GrantFiled: October 1, 1997Date of Patent: February 27, 2001Assignee: Micron Electronics, Inc.Inventors: Michael G. Henderson, Carlton G. Amdahl, Dennis H. Smith, Don Agneta
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Patent number: 6175490Abstract: A network server includes removable network interface modules mounted in a chassis. The network interface modules connect to a CPU through an interconnection assembly module. The network interface modules may comprise removable canisters containing a plurality of interface cards.Type: GrantFiled: October 1, 1997Date of Patent: January 16, 2001Assignee: Micron Electronics, Inc.Inventors: Stephen E. J. Papa, Carlton G. Amdahl, Michael G. Henderson, Don Agneta, Don Shiro, Dennis H. Smith