Abstract: A wideband fast-hopping receiver front-end uses direct digital synthesis (DDS) to provide quadrature LO signals to the front-end's mixers. A DDS circuit stores multiple digital word sequences which represent desired waveforms, and outputs desired sequence pairs to a pair of DACs in response to a clock signal and a command signal. The DACs convert the sequences to analog signals, which are filtered and squared as necessary to provide quadrature LO signals to the mixers. Frequency hopping is accomplished by changing the command signal, which causes a different pair of sequences to be output and the frequency of the LO signals provided to the mixers to be changed. Active image rejection is combined with DDS LO generation to provide faster frequency hopping. The front-end is combined with an ADC and a communications signal processor to provide a complete system, all of which can be integrated together on a common substrate.

Abstract: An RF transceiver with a low power chirp acquisition mode includes a pulse detection circuit, which initiates a low power chirp acquisition mode when an appropriate input pulse is received. While in chirp acquisition mode, all transceiver circuitry not required to determine the chirp rate is powered down, a low power fast-hopping LO generator is powered up to provide one or more LO signals to demodulate the incoming signal, and an active bandpass filter connected to filter the demodulated output is arranged to extend the width of its passband to include the chirp rate. The filtered signal is digitized with an ADC and processed to determine the incoming signal's chirp rate. The low power LO generator comprises a look-up table which provides a plurality of digital output word sequences, each of which represents a discrete LO frequency, to a sine-weighted DAC. The resulting varying frequency analog output signal is multiplied to produce the discrete LO signals needed to demodulate the input signal.

Abstract: An RF transceiver with a low power chirp acquisition mode includes a pulse detection circuit, which initiates a low power chirp acquisition mode when an appropriate input pulse is received. While in chirp acquisition mode, all transceiver circuitry not required to determine the chirp rate is powered down, a low power fast-hopping LO generator is powered up to provide one or more LO signals to demodulate the incoming signal, and an active bandpass filter connected to filter the demodulated output is arranged to extend the width of its passband to include the chirp rate. The filtered signal is digitized with an ADC and processed to determine the incoming signal's chirp rate. The low power LO generator comprises a look-up table which provides a plurality of digital output word sequences, each of which represents a discrete LO frequency, to a sine-weighted DAC. The resulting varying frequency analog output signal is multiplied to produce the discrete LO signals needed to demodulate the input signal.

Abstract: A high performance ADC apparatus. The inventive apparatus comprises a front end ADC baseline device providing a baseline bit size at a baseline data rate and a selected dynamic range at a baseline clock rate. A first circuit is enabled for translating upward, by a selected factor, a reference clock to produce the baseline clock rate. A second circuit is enabled for decimating the baseline data rate of the baseline device to a data rate reduced by the selected factor, so as to achieve an oversampling rate equal to the selected factor. A final circuit is employed for producing an output data rate less than the baseline clock rate by the selected factor with the final resolution.

Abstract: A low noise, low distortion radio frequency amplifier which includes a bootstrap design to minimize intermodulation distortion while simultaneously achieving low noise and wide bandwidth. In the illustrative embodiment, the invention includes a first circuit for receiving an input signal; a second circuit for amplifying the input signal using a transistor Q2; and a third circuit for regulating a rate of change of voltage across the transistor Q2 such that the rate of voltage change is zero. The third circuit includes a transistor Q3 connected to the transistor Q2 in cascode. In the specific illustrative embodiment, the third circuit further includes two diodes D1 and D2 used to modulate the voltage at the input of the transistor Q3 in proportion to the voltage modulation at the input of the transistor Q2. In the illustrative embodiment, the second circuit includes a transistor Q1 connected in cascade to the transistor Q2.

Abstract: A transceiver has a digital signal processor which can insert calibration signals of known level and frequency into transmitters for calibration and correction of transmitter parameters. An output of the calibrated and corrected transmitter is subsequently coupled into a calibration mixer along with a mixing signal (e.g., from a local oscillator generator. The outputs of the calibration mixer have known levels and frequencies and are inserted into receivers for calibration and correction of receiver parameters.

Abstract: A "gain control differential pair" (GCDP) conducts current in response to a differential drive signal, with the gain of a signal path formed via the current circuit of one of its transistors controlled by the drive signal. The GCDP is preferably driven with a drive circuit that receives a symmetrical input signal and produces an offset differential drive signal which has the effect of keeping one of the GCDP's transistors turned off over a wider portion of a symmetrical input signal's voltage range, thereby reducing GCDP-caused noise. One or more GCDPs are implemented as part of a Gilbert mixer to regulate the amount of RF current that flows between the mixer's output and input stages, which eliminates the need to provide gain control in other circuits fed by the mixer. When driven with an offset drive signal, the Gilbert mixer simultaneously provides gain control, low distortion, low power consumption and excellent LO/RF isolation.

Abstract: Mixer structures are described which include a current mirror for insertion of trickle currents to an input differential amplifier and an output interface for coupling an output differential amplifier to an output port. The current mirror trickle currents improve the mixer's conversion gain and third-order intercept point and the current mirror introduces them without introducing spurious signals. The output interface couples mixer currents to the output port while isolating the output port from power-supply spurious signals.

Abstract: An amplifier includes an amplifying circuit and bias current circuit. The bias current circuit includes a beta matching circuit which employs a temperature compensated current reference to develop a bias current for the amplifying circuit. The beta matching circuit is connected to track the current gains of transistors within the amplifying circuit and to thereby provide a temperature compensated bias current to the amplifying circuit. The bias current maintains a fixed bias point regardless of temperature-induced, or other, variations of the current gains of the amplifying circuit's transistors.

Abstract: A low voltage analog front end (AFE) includes a differential transistor pair which converts an input voltage, typically A.C.-coupled to the pair's control inputs, to a differential current. Impedance networks connected to each transistor's control input are joined together at a common node, and a current source is connected to the node which causes DC bias currents to be mirrored through the pair's current circuits, so that the AFE's differential output current comprises a differential current produced by the pair in response to an input voltage and superimposed on the DC bias currents. The current source preferably generates mirrored currents which are larger than its reference current to linearize the pair's response and to provide the AFE with a wide dynamic range. An input to the AFE sees a low impedance which is about equal to the sum of the impedance networks, which can be resistive or complex as needed.

Abstract: A non-attenuating automatic variable gain amplifier (VGA) circuit includes an operational amplifier (op amp) with a feedback resistor connected between its output and inverting input terminals. A variable gain setting resistance circuit having a variable resistance is the gain setting resistor positioned between the op amp's inverting input and a low voltage supply. By varying the resistance of the variable resistance circuit, the gain of the VGA circuit can be manipulated without requiring attenuation of the input signal. A resistance setting control for the variable resistance circuit can operate open loop, fed back from the amplifier output, or fed forward from the amplifier input.

Abstract: A transmit/receive element having a transmit/receive circuit that includes a variable frequency transmit phase lock loop and a variable frequency receive phase lock loop, and an output amplifier that receives a modulated transmit signal from the transmit phase lock loop for driving an antenna element. The transmit phase lock loop receives a feedback signal which is (a) the modulated transmit signal during receive intervals and (b) the output of the output amplifier during transmit intervals, such that the transmit phase lock loop is controlled by a feedback signal at all times.

Abstract: A digital radio frequency (RF) or intermediate frequency (IF) receiver for frequency division multiplexed (FDM) signals contained in a predetermined FDM band including an RF amplifier, an RF bandpass anti-alias filter, and an analog-to-digital (A/D) converter. The sample frequency F.sub.s of the A/D converter is lower than the lowest frequency in the predetermined FDM band and is selected to meet certain specified conditions based on the passband and stop band edges of the anti-alias filter so that the output of the A/D converter contains a non-distorted aliased frequency down converted digital version of the predetermined FDM band which is located between 0 Hz and one-half the sampling frequency. A digital complex mixer responsive to the digital output of the A/D converter translates the spectrum of the sampled digital received signal to center the desired FDM channel at zero frequency (DC).

Abstract: A digital intermediate frequency (IF) receiver for frequency division multiplexed (FDM) signals including analog circuitry for receiving FDM signals and an analog-to-digital (A/D) converter for converting the received signals to a sampled digital received signal. A digital complex mixer responsive to the digital output of the A/D converter translates the spectrum of the sampled digital received signal to center the desired FDM channel at zero frequency (DC). Digital low pass filtering isolates the desired channel centered at DC, and a digital complex mixer can be used to translate the isolated selected channel to a predetermined IF frequency. The in-phase portion of the digital IF centered selected channel or the DC centered complex envelope selected channel can then be provided to appropriate demodulation or decoder networks.

Abstract: A microelectronic package for the protection, housing, cooling and interconnection of a microelectronic chip. The package is made of a plurality of ceramic layers, each of which carries a particular electrically conductive pattern and which have interior openings therein so as to provide recesses in which the chip and discrete capacitors can be located and connected.

Abstract: A window comparator latch network is disclosed for track or sampling a differential input signal and for "latching" the input signal upon a clock signal. Several latch networks are disclosed for both single and dual differential input configurations. The dual input configuration includes first and second pairs of differential transistors which are coupled to a differential regenerative and latching pair of transistors. The regenerative and latching transistor pair provides an output signal having first or second states only upon the required clock signal being applied to a current switching transistor pair. Negative differential signals applied to both first and second pairs of differential transistors results in a "0" logic state output signal from the regenerative and latching transistors. A positive differential signal results in a logic "1" output state. Positive input signals applied to both differential transistors results in a logic "0" output state.

Abstract: A quantizer network is disclosed for decoding an analog signal and providing a four-bit digital output. The analog input signal is divided or quantized into sixteen discrete voltage ranges and applied to sixteen differential amplifiers. Each amplifier has a different reference which must be exceeded before it provides an output signal. The sixteen differential amplifiers are connected to nine latch networks which respond to the signals from the amplifiers and provide a cyclic code in response thereto. The latch networks are connected to a network of logic gates which decode the cycle code into a four-bit digital output signal. The output signals from the logic gate network are applied to output stages which extend the valid time of the output signal from the logic gates.

Abstract: Diodes having a fast response time are used in an Emitter-Coupled Logic (ECL) current switch circuit to cause the injection of an idle current in each of the transistors of said switch. The injection of the idle current through these transistors causes them to operate at all times in an active region. When the transistors remain in the active operating region and are subjected to a switching transient, the parasitic capacitance associated with emitter base and collector base junctions are not charged and discharged to the same extent that they would be if the transistor was turned off completely. Moreover, if the transistors are held on, delay required for minority profile "buildup" in the base region is reduced and the current switch's propagation delay is reduced.