Abstract: A pipelined programmable digital pulse delay system (10) that is capable of processing multiple input pulses simultaneously, each with a unique programmed delay value, includes a plurality of pulse delay units (12, 14, 16), a plurality of buffer registers (18, 20, 22, 24), and a commutator unit 26. The buffer registers (18, 20, 22, 24) each store a delay control word corresponding to a single pulse currently being processed in the system (10). The plurality of pulse delay units (12, 14, 16) each reference a corresponding buffer register (18, 20, 22, 24) for an appropriate delay control value when a particular pulse is about to be received by the pulse delay unit. After the pulse has passed an operative point in the pulse delay unit, the unit then retrieves a delay control value from another buffer register (18, 20, 22, 24) for use with a next input pulse. Thus, pipelined operation is achieved in the system (10).