Abstract: In one embodiment, a clock pulse width control circuit, comprises a plurality of timer circuits to generate a corresponding plurality of delayed pulse signals from an input clock signal, a corresponding plurality of AND gates, each AND gate generating an output signal from a delayed pulse signal and the input clock signal, and a selection circuit to select one of the output signals.

Abstract: In one embodiment, a clock pulse width control circuit, comprises a plurality of timer circuits to generate a corresponding plurality of delayed pulse signals from an input clock signal, a corresponding plurality of AND gates, each AND gate generating an output signal from a delayed pulse signal and the input clock signal, and a selection circuit to select one of the output signals.

Abstract: A system and method are disclosed which provide an integrated circuit having a clock signal that is dynamically manipulated in response to detected events within the integrated circuit. In one embodiment, the chip includes event detection circuitry that monitors the operation of the chip and detects events that lead to a power disturbance therein. Circuitry may be included for detecting anticipated operation known to trigger an event, as well as for detecting unanticipated events. Additionally, clock manipulator circuitry is included to manipulate the chip's clock signal responsive detection of an event to enable the chip to cope with such event. In response to an event being detected, the clock manipulator circuitry may dynamically manipulate the clock signal in various manners, such as by altering the clock signal's duty cycle, delaying the occurrence of a transition of the clock signal, or altering the clock signal's frequency, as examples.

Abstract: Two synchronizing flip-flops synchronize the transitions of a slow clock to a fast clock. The state of a version of the synchronized slow clock is stored by a last-state flip-flop that is clocked on an edge of the fast clock. The last-state flip-flop is compared by logic to a version of the synchronized slow clock to produce a pulse with a width determined by either a phase of the fast clock or a cycle of the fast clock.

Abstract: A system and method are disclosed which utilize an on-chip oscillator to provide the appropriate clock frequency for components of the chip to manage power consumption by the chip. More specifically, in a preferred embodiment of the present invention, an on-chip oscillator is utilized to provide the clock frequency for the chip's core circuitry, and such oscillator can dynamically adjust such clock frequency to manage the chip's power consumption. Thus, such on-chip oscillator generates the processor clock instead of the usual synchronous, externally controlled clock generator. A preferred embodiment of the present invention utilizes a voltage controlled frequency oscillator to control the chip's clock frequency in order to dynamically manage power consumption by the chip. Such oscillator is preferably operable to adjust its output frequency based on the voltage supplied to such oscillator to effectively manage the chip's power consumption.

Abstract: A system and method are disclosed that utilize analog detection of an integrated circuit's (“chip's”) power consumption to enable power consumption management. On-chip circuitry may be utilized to detect analog electrical characteristics of the chip, such as its voltage, from which the chip's power consumption is determined. One embodiment utilizes on-chip circuitry to manage long-term, sustained power consumption of the chip, which encompasses power consumption for approximately a microsecond, as well as more extended time frames. Another embodiment utilizes on-chip circuitry to manage short-term power consumption of the chip, which encompasses power consumption for less than a microsecond (e.g., nanosecond time frame). A preferred embodiment implements both the circuitry for managing long-term power consumption and the circuitry for managing short-term power consumption.

Abstract: A processor in accordance with the present invention includes memory that stores test data and control data. The processor also includes a test application that transmits the test data and the control data from the processor's memory to a test access port of the processor. The test access port then utilizes the test data and the control data to capture state data that defines at least one state of the processor while the processor is executing. This test data may be analyzed via conventional techniques to detect and isolate errors in the execution of the processor.

Abstract: A system and method are disclosed which utilize an on-chip oscillator to provide the appropriate clock frequency for components of the chip to manage power consumption by the chip. More specifically, in a preferred embodiment of the present invention, an on-chip oscillator is utilized to provide the clock frequency for the chip's core circuitry, and such oscillator can dynamically adjust such clock frequency to manage the chip's power consumption. Thus, such on-chip oscillator generates the processor clock instead of the usual synchronous, externally controlled clock generator. A preferred embodiment of the present invention utilizes a voltage controlled frequency oscillator to control the chip's clock frequency in order to dynamically manage power consumption by the chip. Such oscillator is preferably operable to adjust its output frequency based on the voltage supplied to such oscillator to effectively manage the chip's power consumption.

Abstract: A system and method are disclosed that utilize analog detection of an integrated circuit's (“chip's”) power consumption to enable power consumption management. On-chip circuitry may be utilized to detect analog electrical characteristics of the chip, such as its voltage, from which the chip's power consumption is determined. One embodiment utilizes on-chip circuitry to manage long-term, sustained power consumption of the chip, which encompasses power consumption for approximately a microsecond, as well as more extended time frames. Another embodiment utilizes on-chip circuitry to manage short-term power consumption of the chip, which encompasses power consumption for less than a microsecond (e.g., nanosecond time frame). A preferred embodiment implements both the circuitry for managing long-term power consumption and the circuitry for managing short-term power consumption.

Abstract: A method and system for managing metal resources in the physical design of integrated circuits is presented. Percent metal usage is allocated for intra-block routing use by each functional block. Power and clock grids are established. Block designers coordinate the locations of signal ports of the blocks so as to avoid blocking any inter-block signals, areas of metal are then reserved for ports and intra-block signals. The inter-block signals are then pre-routed, avoiding the power grid, clock grid, and reserved intra-block routing metal. If any problem nets emerge from the pre-routing, better port locations and sub-block placement within the respective blocks are determined and the process is repeated.

Abstract: Integrated circuitry comprises target circuitry and test circuitry. The target circuitry uses a clock signal to transfer a target signal within the integrated circuitry. The test circuitry samples the target signal at a selected time from a plurality of possible times within a clock cycle of the clock signal. The test circuitry samples the target signal in response to a test signal indicating the selected time.

Abstract: A test system for a digital integrated circuit in which internal states of the integrated circuit are captured non-destructively while the digital circuit is operating at normal clock speed. Cells for capturing states are sequentially connected into shift registers. Once internal states are latched within cells, the captured states are serially shifted out a test port while the integrated circuit continues to operate. State sampling is triggered internally via a software command or externally via an external signal synchronized to an internal clock.