Patents by Inventor Don D. Reed

Don D. Reed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9037892
    Abstract: An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: May 19, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul W. Coteus, Alan Gara, Thomas M. Gooding, Rudolf A. Haring, Gerard V. Kopcsay, Thomas A. Liebsch, Don D. Reed
  • Patent number: 8595554
    Abstract: Fixing a problem is usually greatly aided if the problem is reproducible. To ensure reproducibility of a multiprocessor system, the following aspects are proposed: a deterministic system start state, a single system clock, phase alignment of clocks in the system, system-wide synchronization events, reproducible execution of system components, deterministic chip interfaces, zero-impact communication with the system, precise stop of the system and a scan of the system state.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ralph A. Bellofatto, Dong Chen, Paul W. Coteus, Noel A. Eisley, Alan Gara, Thomas M. Gooding, Rudolf A. Haring, Philip Heidelberger, Gerard V. Kopcsay, Thomas A. Liebsch, Martin Ohmacht, Don D. Reed, Robert M. Senger, Burkhard Steinmacher-Burow, Yutaka Sugawara
  • Patent number: 8412974
    Abstract: A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: April 2, 2013
    Assignee: International Business Machines Corporation
    Inventors: Dong Chen, Matthew R. Ellavsky, Ross L. Franke, Alan Gara, Thomas M. Gooding, Rudolf A. Haring, Mark J. Jeanson, Gerard V. Kopcsay, Thomas A. Liebsch, Daniel Littrell, Martin Ohmacht, Don D. Reed, Brandon E. Schenck, Richard A. Swetz
  • Publication number: 20120266008
    Abstract: An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.
    Type: Application
    Filed: April 13, 2011
    Publication date: October 18, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul W. Coteus, Alan Gara, Thomas M. Gooding, Rudolf A. Haring, Gerard V. Kopcsay, Thomas A. Liebsch, Don D. Reed
  • Patent number: 8001401
    Abstract: An apparatus and method for controlling power usage in a computer includes a plurality of computers communicating with a local control device, and a power source supplying power to the local control device and the computer. A plurality of sensors communicate with the computer for ascertaining power usage of the computer, and a system control device communicates with the computer for controlling power usage of the computer.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: August 16, 2011
    Assignee: International Business Machines Corporation
    Inventors: Ralph E. Bellofatto, Paul W. Coteus, Paul G. Crumley, Alan G. Gara, Mark E. Giampapa, Thomas M. Gooding, Rudolf A. Haring, Mark G. Megerian, Martin Ohmacht, Don D. Reed, Richard A. Swetz, Todd Takken
  • Publication number: 20110119521
    Abstract: Fixing a problem is usually greatly aided if the problem is reproducible. To ensure reproducibility of a multiprocessor system, the following aspects are proposed: a deterministic system start state, a single system clock, phase alignment of clocks in the system, system-wide synchronization events, reproducible execution of system components, deterministic chip interfaces, zero-impact communication with the system, precise stop of the system and a scan of the system state.
    Type: Application
    Filed: May 5, 2010
    Publication date: May 19, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ralph A. Bellofatto, Dong Chen, Paul W. Coteus, Noel A. Eisley, Alan Gara, Thomas M. Gooding, Rudolf A. Haring, Philip Heidelberger, Gerard V. Kopcsay, Thomas A. Liebsch, Martin Ohmacht, Don D. Reed, Robert M. Senger, Burkhard Steinmacher-Burow, Yutaka Sugawara
  • Publication number: 20110119475
    Abstract: A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.
    Type: Application
    Filed: January 29, 2010
    Publication date: May 19, 2011
    Applicant: International Business Machines Corporation
    Inventors: Dong Chen, Matthew R. Ellavsky, Ross L. Franke, Alan Gara, Thomas M. Gooding, Rudolf A. Haring, Mark J. Jeanson, Gerard V. Kopcsay, Thomas A. Liebsch, Daniel Littrell, Martin Ohmacht, Don D. Reed, Brandon E. Schenck, Richard A. Swetz
  • Patent number: 7941681
    Abstract: Proactive power management in a parallel computer, the parallel computer including a service node and a plurality of compute nodes, the service node connected to the compute nodes through an out-of-band service network, each compute node including a computer processor and a computer memory operatively coupled to the computer processor. Embodiments include receiving, by the service node, a user instruction to initiate a job on an operational group of compute nodes in the parallel computer, the instruction including power management attributes for the compute nodes; setting, by the service node in accordance with the power management attributes for the compute nodes of the operational group, power consumption ratios for each compute node of the operational group including a computer processor power consumption ratio and a computer memory power consumption ratio; and initiating, by the service node, the job on the compute nodes of the operational group of the parallel computer.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: May 10, 2011
    Assignee: International Business Machines Corporation
    Inventors: Thomas M. Gooding, Todd A. Inglett, Thomas A. Liebsch, Thomas E. Musta, Don D. Reed
  • Publication number: 20090049313
    Abstract: Proactive power management in a parallel computer, the parallel computer including a service node and a plurality of compute nodes, the service node connected to the compute nodes through an out-of-band service network, each compute node including a computer processor and a computer memory operatively coupled to the computer processor. Embodiments include receiving, by the service node, a user instruction to initiate a job on an operational group of compute nodes in the parallel computer, the instruction including power management attributes for the compute nodes; setting, by the service node in accordance with the power management attributes for the compute nodes of the operational group, power consumption ratios for each compute node of the operational group including a computer processor power consumption ratio and a computer memory power consumption ratio; and initiating, by the service node, the job on the compute nodes of the operational group of the parallel computer.
    Type: Application
    Filed: August 17, 2007
    Publication date: February 19, 2009
    Inventors: Thomas M Gooding, Todd A. Inglett, Thomas A. Liebsch, Thomas E. Musta, Don D. Reed
  • Publication number: 20090006873
    Abstract: An apparatus and method for controlling power usage in a computer includes a plurality of computers communicating with a local control device, and a power source supplying power to the local control device and the computer. A plurality of sensors communicate with the computer for ascertaining power usage of the computer, and a system control device communicates with the computer for controlling power usage of the computer.
    Type: Application
    Filed: June 26, 2007
    Publication date: January 1, 2009
    Applicant: International Business Machines Corporation
    Inventors: Ralph E. Bellofatto, Paul W. Coteus, Paul G. Crumley, Alan G. Gara, Mark E. Giampapa, Thomas M. Gooding, Rudolf Haring, Mark G. Megerian, Martin Ohmacht, Don D. Reed, Richard A. Swetz, Todd Takken