Patents by Inventor Don G. Craven

Don G. Craven has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for implementing a register scan process
    Patent number: 6732261
    Abstract: In one embodiment, the invention is a method. The method includes receiving expected values of a configuration. The method also includes comparing the expected values with values of a configuration database. Furthermore, the method includes reporting results of the comparing.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: May 4, 2004
    Assignee: Intel Corporation
    Inventors: William J. Chalmers, Joseph A. Schaefer, Kimberly A. Davis, Don G. Craven, Daniel A. Rich
  • METHOD AND APPARATUS FOR IMPLEMENTING A REGISTER SCAN PROCESS
    Publication number: 20030182545
    Abstract: In one embodiment, the invention is a method. The method includes receiving expected values of a configuration. The method also includes comparing the expected values with values of a configuration database. Furthermore, the method includes reporting results of the comparing.
    Type: Application
    Filed: December 30, 1999
    Publication date: September 25, 2003
    Inventors: WILLIAM J. CHALMERS, JOSEPH A. SCHAEFER, KIMBERLY A. DAVIS, DON G. CRAVEN, DANIEL A. RICH
  • Zero connection for on-chip testing
    Patent number: 6605952
    Abstract: In order to make a connection to a test bus on a printed circuit board within a system or platform for the purpose of testing circuits within the system, a regular pattern of contact points which are coupled to the circuits to be tested are formed on the printed circuit board. The contact points are contacted with a plurality of spring loaded contacts, supported in a pattern which is the same as the pattern of contact points, with the spring loaded contacts being coupled to test equipment for testing the circuits.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: August 12, 2003
    Assignee: Intel Corporation
    Inventors: Don G. Craven, Joe A. Harrison
  • Zero connection for on-chip testing
    Publication number: 20030001599
    Abstract: In order to make a connection to a test bus on a printed circuit board within a system or platform for the purpose of testing circuits within the system, a regular pattern of contact points which are coupled to the circuits to be tested are formed on the printed circuit board. The contact points are contacted with a plurality of spring loaded contacts, supported in a pattern which is the same as the pattern of contact points, with the spring loaded contacts being coupled to test equipment for testing the circuits.
    Type: Application
    Filed: June 27, 2001
    Publication date: January 2, 2003
    Inventors: Don G. Craven, Joe A. Harrison