Abstract: The specification describes a new and improved Schottky-gate field-effect transistor (FET) and process for fabricating same wherein selective and multiple ion implanatation doping steps are used to form source, drain and channel regions in a semiconductor body. The semiconductor body is then selectively etched to expose the source and drain regions previously formed, while leaving intact a mesa-shaped, high resistivity stabilizing region of the semiconductor body overlying and electrically stabilizing the ion-implanted channel region. The semiconductor body is then partially passivated with a chosen dielectric layer having two openings therein for exposing source and drain regions, respectively, and a third opening which is aligned with the channel region. Ohmic contacts are deposited in the source and drain openings, and thereafter a V-shaped groove is etched in the mesa-shaped region overlying the channel region to expose a very small area of the channel region.

Abstract: The specification describes a new and improved Schottky-gate field-effect transistor (FET) and process for fabricating same wherein selective and multiple ion implantation doping steps are used to form source, drain and channel regions in a semiconductor body. The semiconductor body is then selectively etched to expose the source and drain regions previously formed, while leaving intact a mesa-shaped, high resistivity stabilizing region of the semiconductor body overlying and electrically stabilizing the ion-implanted channel region. The semiconductor body is then partially passivated with a chosen dielectric layer having two openings therein for exposing source and drain regions, respectively, and a third opening which is aligned with the channel region. Ohmic contacts are deposited in the source and drain openings, and thereafter a V-shaped groove is etched in the mesa-shaped region overlying the channel region to expose a very small area of the channel region.

Abstract: The specification describes new high frequency ion implanted semiconductor devices, novel microwave integrated circuits employing same, and a planar fabrication process for both wherein initially an ion implantation and PN junction passivation mask is formed on one surface of a semiconductor substrate. Next a heavily doped buried region is ion implanted through an opening in the mask and into the substrate to a preselected controlled depth. Thereafter, one or more additional ion implants are made through the mask opening to complete the active device regions and a PN junction therebetween, all of which are bounded by an annular, higher resistivity unimplanted region of the semiconductor substrate.

Abstract: Disclosed are new high frequency ion implanted passivated semiconductor devices and a planar fabrication process therefor wherein initially an ion implantation and PN junction passivation mask is formed on one surface of a semiconductor crystal. Thereafter, one or more conductivity type determining ion species are implanted through an opening in the mask and into the semiconductor crystal to form active device regions including a PN junction, all of which are bounded by an annular, higher resistivity unimplanted region of the semiconductor crystal. The PN junction thus formed terminates beneath the implantation and passivation mask, and the semiconductor crystal is then annealed to remove ion implantation damage and to electrically activate the ion implanted regions, while simultaneously controlling the lateral movement of the PN junction beneath the passivation mask.

Abstract: The specification describes new high frequency ion implanted semiconductor devices, novel microwave integrated circuits employing same, and a planar fabrication process for both wherein initially an ion implantation and PN junction passivation mask is formed on one surface of a semiconductor substrate. Next, a heavily doped buried region is ion implanted through an opening in the mask and into the substrate to a preselected controlled depth. Thereafter, one or more additional ion implants are made through the mask opening to complete the active device regions and a PN junction therebetween, all of which are bounded by an annular, higher resistivity unimplanted region of the semiconductor substrate.