Abstract: A phase lock loop including a time-to-digital converter, a period counter, a phase accumulator, a comparator, and an output unit is disclosed. The time-to-digital converter outputs a detected phase error based on the timing difference between a reference clock signal and an output clock signal. The period counter increases a first accumulative value in each period of the output clock signal. The phase accumulator increases a second accumulative value in each period of the reference clock signal and outputs the second accumulative value as an estimative phase error between the reference clock signal and the output clock signal in next period. The comparator outputs a frequency correction signal according to the detected phase error, the first accumulative value, and the estimative phase error. The output unit provides the output clock signal and adjusts its frequency according to the frequency correction signal.