Abstract: In accordance with an embodiment of the disclosed matter, a voltage regulator may supply power to a component within a computer system. A timer may be provided. The voltage regulator may operate synchronously, and when the timer expires the voltage regulator may operate non-synchronously. For one embodiment, the voltage regulator may operate non-synchronously when the timer expires and the component is in a sleep state.

Abstract: A computer system includes a voltage regulator that supplies power to a component. The component may provide a signal indicating an amount of current the component consumes under a high utilization operating condition. The voltage regulator may then determine the slope of a load line using this signal.

Abstract: Briefly, descriptions of embodiments for, at least practically, reducing the power consumption of a mass storage device are provided. The present disclosure relates to at least partially reducing the power consumption of a mass storage device and, more particularly, to a method and device for at least partially reducing the power consumption of a mass storage device. One embodiment may include a power supply coupled with at least one mass storage device, and a control circuit. The control circuit may be capable of at least partially dynamically adjusting the amount of electrical power supplied to the mass storage device based, at least in part, upon at least one signal provided to the control circuit.

Abstract: A computer system having one or more components capable of being in either wake or sleep states includes a power manager and a voltage regulator. The power manager may generate a power state signal indicating the power state of the component, and this signal may be provided to the voltage regulator. The voltage regulator may supply power to the component. The target voltage level of the power may be dependent on both a current level of the power and the power state signal.

Abstract: Power is applied to a voltage supply. A signal that indicates reduced work capability in an integrated circuit (IC) that is being powered by the voltage supply is generated based on workload demand or conscious power and performance tradeoffs. This signal is applied to increase the power efficiency of the voltage supply, while the supply is powering the IC in its reduced work capability state.

Abstract: For one embodiment of the present invention, a processor may include one or more integrated voltage regulators powered by an external voltage regulator and generating one or more local supply voltages for the processor. The one or more local supply voltages may be set to allow one or more circuits powered by the local supply voltage(s) to meet a timing requirement. The local supply voltage(s) may be adjusted by the processor in accordance with a power management policy.

Abstract: A computer system having multiple components capable of being in either a wake or sleep state includes a power manager and a voltage regulator. The power manager may generate a power state status signal indicating the power states of the components, and this signal may be provided to the voltage regulator. In response, the voltage regulator may operate in a synchronous mode when the power state status signal indicates that the components are in a wake state. The voltage regulator may operate in a non-synchronous mode when the power state status signal indicates that the components are in a sleep state.

Abstract: A computer system having multiple components capable of being in either a wake or sleep state includes a controller and a voltage regulator. The controller may generate a power state status signal indicating the power states of the components, and this signal may be provided to the voltage regulator. In response, the voltage regulator increases its output voltage level to the components when the power state status signal indicates that the components enter a sleep state.

Abstract: According to one embodiment of the present invention, a voltage regulator is disclosed. The voltage regulator includes a step-down portion to step down an input voltage to a desired voltage when the input voltage is provided by a battery power source; and a step-up portion to step up the input voltage to the desired voltage when the input voltage is provided by a system rail. In accordance with another embodiment of the present invention, the voltage regulator provides power to a display device such as an LCD, a flat panel display, a plasma screen, and a TFT display.

Abstract: According to one embodiment, a method of power management for a computer system having a display may include identifying at least one area of interest displayed on a display screen. The area of interest may be a selected window. Color of at least one pixel not associated with the area of interest may be adjusted to a new color that consumes less power than an intended color. This new color may be white when the display is a normally white liquid crystal display (LCD).

Abstract: According to one embodiment, a system is disclosed. The system includes a battery, a super-capacitor (SC) coupled in parallel to the battery, a computer system coupled to the battery and the SC, and a current limiter coupled to the battery the SC and the computer system. The current limiter prevents excess current from flowing from the battery to the SC.

Abstract: According to one embodiment of the present invention, a method of power management for a computer system using an organic light-emitting diode (OLED) display is disclosed. The method includes identifying a selected window and one or more non-selected windows. Picture elements (pixels) associated with the selected window are then enabled to emit light. Pixels associated with the one or more non-selected windows are prevented from emitting as much light as the pixels associated with the selected window.

Abstract: In accordance with an embodiment of the disclosed matter, a voltage regulator may supply power to a component within a computer system. A timer may be provided. The voltage regulator may operate synchronously, and when the timer expires the voltage regulator may operate non-synchronously. For one embodiment, the voltage regulator may operate non-synchronously when the timer expires and the component is in a sleep state.

Abstract: In accordance with an embodiment of the disclosed matter, a voltage regulator may supply power to a component within a computer system. A timer may be provided. The voltage regulator may operate synchronously, and when the timer expires the voltage regulator may operate non-synchronously. For one embodiment, the voltage regulator may operate non-synchronously when the timer expires and the component is in a sleep state.

Abstract: Power is applied to a voltage supply. A signal that indicates reduced work capability in an integrated circuit (IC) that is being powered by the voltage supply is generated based on workload demand or conscious power and performance tradeoffs. This signal is applied to increase the power efficiency of the voltage supply, while the supply is powering the IC in its reduced work capability state.

Abstract: Methods and systems of providing power to a central processing unit (CPU) provide for enhanced surge protection during CPU current consumption going from high current to low current consumption. In one approach, a circuit as a power output stage with an output node, and a controller circuit coupled to the power output stage. The controller circuit selectively switches the power output stage into a current ramp down mode based on detection of a voltage surge at the output node. The power output stage has an associated current ramp down rate. The CPU is coupled to the output node and a surge notification input of the power output stage, where the power output stage accelerates the current ramp down based on a notification signal from the CPU for a duration proportional to the change in CPU current consumption from high to low current consumption.

Abstract: Methods and systems of providing power to a central processing unit (CPU) provide for enhanced surge protection and increased battery life. In one approach, an integrated circuit as a power output stage with an output node, and a voltage regulator coupled to the power output stage. The voltage regulator selectively switches the power output stage into a current ramp down mode based on detection of a voltage surge at the output node. The power output stage has an associated current ramp down rate. The CPU is coupled to the output node and a surge notification input of the power output stage, where the power output stage accelerates the current ramp down based on a notification signal from the CPU.

Abstract: A system including at least one electronic component and a battery check circuit. When a power consumption level of the at least one electronic component is increased, the battery check circuit determines whether to provide power from a battery to the at least one electronic component by comparing a power level of the battery to a first power level.

Abstract: Power is applied to a voltage supply. A signal that indicates reduced work capability in an integrated circuit (IC) that is being powered by the voltage supply is generated based on workload demand or conscious power and performance tradeoffs. This signal is applied to increase the power efficiency of the voltage supply, while the supply is powering the IC in its reduced work capability state.

Abstract: In accordance with an embodiment of the disclosed matter, a voltage regulator may supply power to a component within a computer system. A timer may be provided. The voltage regulator may operate synchronously, and when the timer expires the voltage regulator may operate non-synchronously. For one embodiment, the voltage regulator may operate non-synchronously when the timer expires and the component is in a sleep state.