Patents by Inventor Don L. Kendall

Don L. Kendall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10675618
    Abstract: Bare porous polymer monoliths, fluidic chips, methods of incorporating bare porous polymer monoliths into fluidic chips, and methods for functionalizing bare porous polymer monoliths are described. Bare porous polymer monoliths may be fabricated ex situ in a mold. The bare porous polymer monoliths may also be functionalized ex situ. Incorporating the bare preformed porous polymer monoliths into the fluidic chips may include inserting the monoliths into channels of channel substrates of the fluidic chips. Incorporating the bare preformed porous polymer monoliths into the fluidic chips may include bonding a capping layer to the channel substrate. The bare porous polymer monoliths may be mechanically anchored to channel walls and to the capping layer. The bare porous polymer monoliths may be functionalized by ex situ immobilization of capture probes on the monoliths. The monoliths may be functionalized by direct attachment of chitosan.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: June 9, 2020
    Assignee: University of Maryland, College Park
    Inventors: Eric L. Kendall, Erik Wienhold, Omid Rahmanian, Don L. Devoe
  • Patent number: 7259099
    Abstract: The present invention provides a MOSFET device comprising: a substrate including a plurality of atomic ridges, each of the atomic ridges including a semiconductor layer comprising Si and an dielectric layer comprising a Si compound; a plurality nanogrooves between the atomic ridges; at least one elongated molecule located in at least one of the nanogrooves; a porous gate layer located on top of the plurality of atomic ridges. The present invention also provides a membrane comprising: a substrate; and a plurality of nanowindows in the substrate and a method for forming nanowindows in a substrate.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: August 21, 2007
    Assignee: Starmega Corporation
    Inventors: Don L. Kendall, Mark J. Guttag
  • Publication number: 20040061103
    Abstract: The present invention provides a quantum structure product comprising a substrate having quantum ridges and quantum tips on at least one surface thereof. In some embodiments of the invention quantum ridges may support quantum wires and the quantum tips may support quantum dots. Grooves which separate the quantum ridges and quantum tips from each other may be shallow or deep, and may contain organic molecules, fullerene tubes, and fullerene balls.
    Type: Application
    Filed: September 30, 2003
    Publication date: April 1, 2004
    Inventor: Don L. Kendall
  • Patent number: 6667492
    Abstract: The present invention provides a quantum structure product comprising a substrate having quantum ridges and quantum tips on at least one surface thereof. In some embodiments of the invention quantum ridges may support quantum wires and the quantum tips may support quantum dots. Grooves which separate the quantum ridges and quantum tips from each other may be shallow or deep, and may contain organic molecules, fullerene tubes, and fullerene balls.
    Type: Grant
    Filed: November 9, 1998
    Date of Patent: December 23, 2003
    Inventor: Don L. Kendall
  • Publication number: 20030127692
    Abstract: The present invention provides a MOSFET device comprising: a substrate including a plurality of atomic ridges, each of the atomic ridges including a semiconductor layer comprising Si and an dielectric layer comprising a Si compound; a plurality nanogrooves between the atomic ridges; at least one elongated molecule located in at least one of the nanogrooves; a porous gate layer located on top of the plurality of atomic ridges. The present invention also provides a membrane comprising: a substrate; and a plurality of nanowindows in the substrate and a method for forming nanowindows in a substrate.
    Type: Application
    Filed: October 10, 2002
    Publication date: July 10, 2003
    Inventor: Don L. Kendall
  • Patent number: 6465782
    Abstract: The present invention provides a multi-tip array device comprising: a substrate; a multi-tip array of atomic tips on the substrate, the multi-tip array having a pitch of 0.94 to 5.4 nm between adjacent tips in at least one direction; and means for moving the substrate. The present invention also provides an atomic claw comprising: a mounting block; a paddle having a multi-tip array thereon, the multi-tip array having a pitch of 0.94 to 5.4 nm between adjacent tips in at least one direction; and a cantilever connected to the paddle and the mounting block, wherein the cantilever allows the paddle to be moved in at least one arcuate direction.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: October 15, 2002
    Assignee: StarMega Corporation
    Inventor: Don L. Kendall
  • Patent number: 4104697
    Abstract: An axial-lead fixed-value capacitor comprising a metal-nitride-oxide-silicon chip in a standard diode package has been fabricated, having capacitance values in the 10 to 1000 pico-farad range. The device features a beveled-edge configuration which contributes to a low leakage current and also facilitates the sealing of the semiconductor chip in a double plug axial-lead package. The double layer dielectric medium comprises a thermally grown silicon oxide film typically 450 angstroms thick, for example, and a plasma deposited layer of silicon nitride typically 350 angstroms thick, for example.
    Type: Grant
    Filed: January 14, 1977
    Date of Patent: August 1, 1978
    Assignee: Texas Instruments Incorporated
    Inventors: Don L. Kendall, Byron T. Ahlburn, Klaus C. Wiemer
  • Patent number: 4017885
    Abstract: Disclosed is a semiconductor capacitor which utilizes the volume of the semiconductor substrate in which it is formed to create increased surface area and thereby to provide increased capacitance. The surface area is increased by forming selectively spaced grooves in the surface of the semiconductor substrate by orientation dependent etches and utilizing the sidewalls of the grooves as surface. Groove depth is limited to a predetermined value by etching time, geometrical constraints, or by etch stops. This provides for precise control of capacitance values on a batch or commercial basis. Increases up to at least 100-fold in capacitance as compared to a flat capacitor structure as possible. A thin layer of dielectric is formed over the increased surface area, and thereafter a conducting layer is formed over the dielectric layer to provide a dielectric capacitor. An active junction P-N capacitor may also be formed.
    Type: Grant
    Filed: December 13, 1974
    Date of Patent: April 12, 1977
    Assignee: Texas Instruments Incorporated
    Inventors: Don L. Kendall, Walter T. Matzen
  • Patent number: 4015175
    Abstract: An axial-lead fixed-value capacitor comprising a metal-nitride-oxide-silicon chip in a standard diode package has been fabricated, having capacitance values in the 10 to 1000 pico-farad range. The device features a beveled-edge configuration which contributes to a low leakage current and also facilitates the sealing of the semiconductor chip in a double plug axial-lead package. The double layer dielectric medium comprises a thermally grown silicon oxide film typically 450 angstroms thick, for example, and a plasma deposited layer of silicon nitride typically 350 angstroms thick, for example.
    Type: Grant
    Filed: June 2, 1975
    Date of Patent: March 29, 1977
    Assignee: Texas Instruments Incorporated
    Inventors: Don L. Kendall, Byron T. Ahlburn, Klaus C. Wiemer
  • Patent number: 3962713
    Abstract: Disclosed is a semiconductor capacitor which utilizes the volume of the semiconductor substrate in which it is formed to create increased surface area and thereby to provide increased capacitance. The surface area is increased by forming selectively spaced grooves in the surface of the semiconductor substrate and utilizing the sidewalls of the grooves as surface. A thin layer of dielectric is formed over the increased surface area, and thereafter a metal layer is formed over the dielectric layer to provide a dielectric capacitor. An active junction P-N capacitor may be formed instead of a dielectric capacitor by forming a P-N junction comprising the increased surface area, and thereover forming the metallized contact.
    Type: Grant
    Filed: October 25, 1973
    Date of Patent: June 8, 1976
    Assignee: Texas Instruments Incorporated
    Inventors: Don L. Kendall, Walter T. Matzen
  • Patent number: 3936789
    Abstract: A spreading-resistance silicon thermistor having high-precision values of resistance and temperature coefficient of resistance (TCR) is produced by a high-volume, low-cost, photolithographic technique, wherein multiple thin-film contacts are tested and selectively trimmed to permit computerized control of precision resistance values in a production-line operation.
    Type: Grant
    Filed: June 3, 1974
    Date of Patent: February 3, 1976
    Assignee: Texas Instruments Incorporated
    Inventors: Walter T. Matzen, Don L. Kendall