Abstract: The present invention provides a MOSFET device comprising: a substrate including a plurality of atomic ridges, each of the atomic ridges including a semiconductor layer comprising Si and an dielectric layer comprising a Si compound; a plurality nanogrooves between the atomic ridges; at least one elongated molecule located in at least one of the nanogrooves; a porous gate layer located on top of the plurality of atomic ridges. The present invention also provides a membrane comprising: a substrate; and a plurality of nanowindows in the substrate and a method for forming nanowindows in a substrate.

Abstract: The present invention provides a quantum structure product comprising a substrate having quantum ridges and quantum tips on at least one surface thereof. In some embodiments of the invention quantum ridges may support quantum wires and the quantum tips may support quantum dots. Grooves which separate the quantum ridges and quantum tips from each other may be shallow or deep, and may contain organic molecules, fullerene tubes, and fullerene balls.

Abstract: The present invention provides a quantum structure product comprising a substrate having quantum ridges and quantum tips on at least one surface thereof. In some embodiments of the invention quantum ridges may support quantum wires and the quantum tips may support quantum dots. Grooves which separate the quantum ridges and quantum tips from each other may be shallow or deep, and may contain organic molecules, fullerene tubes, and fullerene balls.

Abstract: The present invention provides a MOSFET device comprising: a substrate including a plurality of atomic ridges, each of the atomic ridges including a semiconductor layer comprising Si and an dielectric layer comprising a Si compound; a plurality nanogrooves between the atomic ridges; at least one elongated molecule located in at least one of the nanogrooves; a porous gate layer located on top of the plurality of atomic ridges. The present invention also provides a membrane comprising: a substrate; and a plurality of nanowindows in the substrate and a method for forming nanowindows in a substrate.

Abstract: The present invention provides a multi-tip array device comprising: a substrate; a multi-tip array of atomic tips on the substrate, the multi-tip array having a pitch of 0.94 to 5.4 nm between adjacent tips in at least one direction; and means for moving the substrate. The present invention also provides an atomic claw comprising: a mounting block; a paddle having a multi-tip array thereon, the multi-tip array having a pitch of 0.94 to 5.4 nm between adjacent tips in at least one direction; and a cantilever connected to the paddle and the mounting block, wherein the cantilever allows the paddle to be moved in at least one arcuate direction.

Abstract: An axial-lead fixed-value capacitor comprising a metal-nitride-oxide-silicon chip in a standard diode package has been fabricated, having capacitance values in the 10 to 1000 pico-farad range. The device features a beveled-edge configuration which contributes to a low leakage current and also facilitates the sealing of the semiconductor chip in a double plug axial-lead package. The double layer dielectric medium comprises a thermally grown silicon oxide film typically 450 angstroms thick, for example, and a plasma deposited layer of silicon nitride typically 350 angstroms thick, for example.

Abstract: Disclosed is a semiconductor capacitor which utilizes the volume of the semiconductor substrate in which it is formed to create increased surface area and thereby to provide increased capacitance. The surface area is increased by forming selectively spaced grooves in the surface of the semiconductor substrate by orientation dependent etches and utilizing the sidewalls of the grooves as surface. Groove depth is limited to a predetermined value by etching time, geometrical constraints, or by etch stops. This provides for precise control of capacitance values on a batch or commercial basis. Increases up to at least 100-fold in capacitance as compared to a flat capacitor structure as possible. A thin layer of dielectric is formed over the increased surface area, and thereafter a conducting layer is formed over the dielectric layer to provide a dielectric capacitor. An active junction P-N capacitor may also be formed.

Abstract: An axial-lead fixed-value capacitor comprising a metal-nitride-oxide-silicon chip in a standard diode package has been fabricated, having capacitance values in the 10 to 1000 pico-farad range. The device features a beveled-edge configuration which contributes to a low leakage current and also facilitates the sealing of the semiconductor chip in a double plug axial-lead package. The double layer dielectric medium comprises a thermally grown silicon oxide film typically 450 angstroms thick, for example, and a plasma deposited layer of silicon nitride typically 350 angstroms thick, for example.

Abstract: Disclosed is a semiconductor capacitor which utilizes the volume of the semiconductor substrate in which it is formed to create increased surface area and thereby to provide increased capacitance. The surface area is increased by forming selectively spaced grooves in the surface of the semiconductor substrate and utilizing the sidewalls of the grooves as surface. A thin layer of dielectric is formed over the increased surface area, and thereafter a metal layer is formed over the dielectric layer to provide a dielectric capacitor. An active junction P-N capacitor may be formed instead of a dielectric capacitor by forming a P-N junction comprising the increased surface area, and thereover forming the metallized contact.

Abstract: A spreading-resistance silicon thermistor having high-precision values of resistance and temperature coefficient of resistance (TCR) is produced by a high-volume, low-cost, photolithographic technique, wherein multiple thin-film contacts are tested and selectively trimmed to permit computerized control of precision resistance values in a production-line operation.