Abstract: A method and apparatus for adjusting charging and discharging currents of a pin driver to optimize slew rates and overshoot for different types of logic circuits. The current charging and discharging circuits include respective transistors that are mirrored to a transistor whose current varies in accordance with VH-VL where VH and VL are programmed reference voltages defining the high and low voltage levels of the output driver pulses. Thus, when VH-VL is relatively large such as for CMOS outputs, slew rates are relatively high. However, when VH-VL is relatively small such as for ECL outputs, slew rates are reduced to prevent excessive overshoot.

Abstract: A test equipment pin driver having a main output channel including a pulse forming circuit, a buffer and an output amplifier connected in series. The pulse forming circuit provides pulses that are timed to a data input signal, and the buffer passes the pulses to the amplifier which produces driver pulses adapted to be transmitted to a device under test. The high and low voltage levels of the driver pulses are made substantially the same as programmed high and low voltages by providing scaled replicas of the buffer and amplifier, and using closed loop compensation to accurately drive the replica outputs to the high and low programmed voltages, respectively. The replicas mirror the DC performance of the buffer and amplifier of the main output channel, and clamping voltages are provided from the closed loops to enable operation of the main output channel in a manner that produces driver pulses with the programmed high and low voltage levels.

Abstract: A pin driver amplifier having a complementary pair of transistors with a pair of resistors coupled between the respective emitters. A node between the resistors is coupled through an output series resistor to an output terminal adapted for connection of a transmission line that conducts driver pulses of predetermined voltage levels and timing to a device under test. A capacitor is tied between the emitters to provide a substantially constant reverse termination impedance for the transmission line thereby reducing reflections. Also, an RC network is coupled between the output terminal and ground to further reduce reflections. The amplifier transistors are driven by respective buffer transistor emitters that are tied together by a capacitor to make the positive and negative going drive capabilities for the amplifier transistors more equal. Further, capacitors are coupled between the amplifier collectors and ground to provide a bypass for parasitic inductance in the supply voltage wires.

Abstract: An isolation circuit (20) that is devoid of coupling transformers and yet suitable for use as a telephone line interface. The circuit is characterized by very wide bandwidth, low noise, and high linearity. Opto-isolators couple analog transmit and receive channels in a user device (12) across an isolation barrier (57) to a line pair for full duplex communication on the line pair. The interface circuit, which also includes a hybrid (55), includes first and second oppositely directed linear optocouplers (50,52). The first is disposed between the transmit channel and the hybrid; the second between the receive channel and the hybrid.