Abstract: An insulation blowing machine is provided, comprising an upper section, comprising a hopper, an agitator, and an agitator motor coupled to drive the agitator; a base, comprising a blower, an airlock, and an airlock motor coupled to drive airlock paddles within the airlock; and a pivoting mechanism connecting the upper section with the base, whereby the upper section is tiltable on the pivoting mechanism away from the base to an open position without disassembly or disengagement of components in the upper section from components in the base to expose the airlock paddles within the airlock; whereby, in operation insulation fed into the hopper passes through an opening in the bottom of the hopper and into the airlock to be discharged through an outlet.

Abstract: An insulation blowing machine is provided, comprising an upper section, comprising a hopper, an agitator, and an agitator motor coupled to drive the agitator; a base, comprising a blower, an airlock, and an airlock motor coupled to drive airlock paddles within the airlock; and a pivoting mechanism connecting the upper section with the base, whereby the upper section is tiltable on the pivoting mechanism away from the base to an open position without disassembly or disengagement of components in the upper section from components in the base to expose the airlock paddles within the airlock; whereby, in operation insulation fed into the hopper passes through an opening in the bottom of the hopper and into the airlock to be discharged through an outlet.

Abstract: An athletic glove having at least one padded insert is provided. The padded insert comprises reticulated or open cell form, or a rubber formed into a matrix that allows ventilation paths.

Abstract: An embodiment includes a process of forming a gate stack that acts to resist the redeposition to the semiconductive substrate of mobilized metal such as from a metal gate electrode. An embodiment also relates to a system that achieves the process. An embodiment also relates to a gate stack structure that provides a composition that resists the redeposition of metal during processing and field use.

Abstract: An embodiment includes a process of forming a gate stack that acts to resist the redeposition to the semiconductive substrate of mobilized metal such as from a metal gate electrode. An embodiment also relates to a system that achieves the process. An embodiment also relates to a gate stack structure that provides a composition that resists the redeposition of metal during processing and field use.

Abstract: The invention includes selective oxidation methods and transistor fabrication methods. In one implementation, a selective oxidation method includes positioning a substrate within a chamber. The substrate has first and second different oxidizable materials. The substrate is therein exposed to a gas mixture comprising an oxidizer and a reducer under conditions effective to selectively grow an oxide layer on the first material relative to the second material. The oxidizer oxidizes the first and second materials under the conditions. The reducer reduces oxidized second material under the conditions back to the second material. After selectively growing the oxide layer on the first material relative to the second material, partial pressure of the oxidizer and the reducer is reduced within the chamber by flowing an inert gas to the chamber while chamber pressure and chamber temperature are at or above those of the conditions during the exposing. Other aspects and implementations are contemplated.

Abstract: An improved capacitor that is less susceptible to the depletion effect and methods for providing the same. The capacitor comprises a first and second electrode and an insulating layer interposed therebetween. The first electrode includes a bulk layer comprising n-doped polysilicon. The first electrode also includes an interface layer extending from a first surface of the bulk layer to the insulating layer. The interface layer is heavily doped with phosphorus so that the depletion region of the first electrode is confined substantially within the interface layer. The method of forming the interface layer comprises depositing a layer of hexamethldisilazane (HMDS) material over the first surface of the bulk layer so that HMDS molecules of the HMDS material chemically bond to the first surface of the bulk layer. The method further comprises annealing the layer of HMDS material in a phosphine ambient so as to replace CH3 methyl groups with PH3 molecules.

Abstract: A transistor gate is formed which comprises semiconductive material and conductive metal. Source/drain regions are formed proximate the transistor gate. In one implementation, the transistor gate and source/drain regions are exposed to a gas mixture comprising H2O, H2, a noble gas and N2 under conditions effective to oxidize outer surfaces of the source/drain regions. The N2 is present in the gas mixture at greater than 0% and less than or equal to 20.0% by volume. In one implementation, the. transistor gate and source/drain regions are exposed to a gas mixture comprising H2O, H2, and an inert gas under conditions effective to oxidize outer surfaces of the source/drain regions. The conditions comprise a pressure of greater than room ambient pressure. Other aspects and implementations are contemplated.

Abstract: Systems and devices are disclosed utilizing a silicon-containing barrier layer. A semiconductor device is disclosed and includes a substrate, a gate oxide, a silicon-containing barrier layer and a gate electrode. The gate oxide is formed over the substrate. The silicon-containing barrier layer is formed over the gate oxide by causing silicon atoms of a precursor layer react with a reactive agent. The gate electrode is formed over the silicon-containing barrier layer.

Abstract: A sidewall oxidation process for use during the formation of a transistor such as a flash memory cell allows for improved control of a gate oxide profile. The method comprises doping transistor source and drain regions to different doping levels, then performing a transistor sidewall oxidation using a particular process to modify the gate oxide thickness. The oxide forms at a faster rate along the source sidewall than along the drain sidewall. By using ranges within the oxidation environment described, a source side gate oxide having a variable and selectable thickness may be formed, while forming a drain-side oxide which has a single thickness where a thinner layer is desirable. This leads to improved optimization of key competing requirements of a flash memory cell, such as program and erase performance, while maintaining sufficient long-term data retention. The process may allow improved cell scalability, shortened design time, and decreased manufacturing costs.

Abstract: Embodiments provide methods and apparatuses for chemical vapor depositing a dielectric film, and various structures, devices, and systems, which incorporate dielectric elements formed from the dielectric film. The method includes heating a chamber, within which a substrate is located, to a temperature sufficient to thermally decompose an oxidizing component. A gas flow is passed over the substrate to deposit the dielectric film. To form an oxide, the gas flow includes a silicon bearing component, the oxidizing component, and a chloride component. The silicon bearing component and the chloride component are distinct from each other. To form an oxynitride, the gas flow further includes an ammonia component. The silicon bearing component can be substituted by a tantalum bearing component or an aluminum bearing component, to form other types of oxynitrides.

Abstract: The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures and a dilute steam ambient, additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. In the preferred embodiment, the interface is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability due to enhanced charge transfer along grain boundaries. At the same time, oxide in an upper storage dielectric layer (oxide-nitride-oxide or ONO) is enhanced in the dilute steam oxidation.

Abstract: An improved capacitor that is less susceptible to the depletion effect and methods for providing the same. The capacitor comprises a first and second electrode and an insulating layer interposed therebetween. The first electrode includes a bulk layer comprising n-doped polysilicon. The first electrode also includes an interface layer extending from a first surface of the bulk layer to the insulating layer. The interface layer is heavily doped with phosphorus so that the depletion region of the first electrode is confined substantially within the interface layer. The method of forming the interface layer comprises depositing a layer of hexamethldisilazane (HMDS) material over the first surface of the bulk layer so that HMDS molecules of the HMDS material chemically bond to the first surface of the bulk layer. The method further comprises annealing the layer of HMDS material in a phosphine ambient so as to replace CH3 methyl groups with PH3 molecules.

Abstract: Processing equipment for forming films exhibiting at least one substantially uniform property on an active surface of a semiconductor substrate includes a component for continuously varying a reaction chamber temperature. The temperature variation component may operate under control of a feedback control system or a temperature regulator, which may be associated with one or more temperature sensors.

Abstract: Systems and devices are disclosed utilizing a silicon-containing barrier layer. A semiconductor device is disclosed and includes a substrate, a gate oxide, a silicon-containing barrier layer and a gate electrode. The gate oxide is formed over the substrate. The silicon-containing barrier layer is formed over the gate oxide by causing silicon atoms of a precursor layer react with a reactive agent. The gate electrode is formed over the silicon-containing barrier layer.

Abstract: Embodiments provide methods and apparatuses for chemical vapor depositing a dielectric film, and various structures, devices, and systems, which incorporate dielectric elements formed from the dielectric film. The method includes heating a chamber, within which a substrate is located, to a temperature sufficient to thermally decompose an oxidizing component. A gas flow is passed over the substrate to deposit the dielectric film. To form an oxide, the gas flow includes a silicon bearing component, the oxidizing component, and a chloride component. The silicon bearing component and the chloride component are distinct from each other. To form an oxynitride, the gas flow further includes an ammonia component. The silicon bearing component can be substituted by a tantalum bearing component or an aluminum bearing component, to form other types of oxynitrides.

Abstract: A transistor gate is formed which comprises semiconductive material and conductive metal. Source/drain regions are formed proximate the transistor gate. In one implementation, the transistor gate and source/drain regions are exposed to a gas mixture comprising H2O, H2, a noble gas and N2 under conditions effective to oxidize outer surfaces of the source/drain regions. The N2 is present in the gas mixture at greater than 0% and less than or equal to 20.0% by volume. In one implementation, the transistor gate and source/drain regions are exposed to a gas mixture comprising H2O, H2, and an inert gas under conditions effective to oxidize outer surfaces of the source/drain regions. The conditions comprise a pressure of greater than room ambient pressure. Other aspects and implementations are contemplated.

Abstract: A process for forming a thin layer exhibiting a substantially uniform property on an active surface of a semiconductor substrate includes varying the temperature within a reaction chamber while a layer of a material is formed upon the semiconductor substrate. Varying the temperature within the reaction chamber facilitates temperature uniformity across the semiconductor wafer. As a result, a layer forming reaction occurs at a substantially consistent rate over the entire active surface of the semiconductor substrate. The process may also include oscillating the temperature within the reaction chamber while a layer of a material is being formed upon a semiconductor substrate.

Abstract: A sidewall oxidation process for use during the formation of a transistor such as a flash memory cell allows for improved control of a gate oxide profile. The method comprises doping transistor source and drain regions to different doping levels, then performing a transistor sidewall oxidation using a particular process to modify the gate oxide thickness. The oxide forms at a faster rate along the source sidewall than along the drain sidewall. By using ranges within the oxidation environment described, a source side gate oxide having a variable and selectable thickness may be formed, while forming a drain-side oxide which has a single thickness where a thinner layer is desirable. This leads to improved optimization of key competing requirements of a flash memory cell, such as program and erase performance, while maintaining sufficient long-term data retention. The process may allow improved cell scalability, shortened design time, and decreased manufacturing costs.

Abstract: The invention includes selective oxidation methods and transistor fabrication methods. In one implementation, a selective oxidation method includes positioning a substrate within a chamber. The substrate has first and second different oxidizable materials. The substrate is therein exposed to a gas mixture comprising an oxidizer and a reducer under conditions effective to selectively grow an oxide layer on the first material relative to the second material. The oxidizer oxidizes the first and second materials under the conditions. The reducer reduces oxidized second material under the conditions back to the second material. After selectively growing the oxide layer on the first material relative to the second material, partial pressure of the oxidizer and the reducer is reduced within the chamber by flowing an inert gas to the chamber while chamber pressure and chamber temperature are at or above those of the conditions during the exposing. Other aspects and implementations are contemplated.