Patents by Inventor Don R. Sauer

Don R. Sauer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7339755
    Abstract: A ring device is adapted for wearing on at least one finger of a user. The ring device includes a wearable main body portion and an optical member that is moveably affixed thereto. The optical member can be positioned in at least two positions: a viewing position, and a storage position. The optical member may be moved relative to the main body portion through a number of positioning mechanisms including: a hinged member, a sliding member, and a rotating member. The viewing position may include any number positions for viewing an object in a field of view. The storage position corresponds to an alignment of the optical member with the main body such that the device is aesthetically pleasing. A face of the main body may include an insignia or other decorative design that is viewable through the optical member, and may optionally be removable by the user.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: March 4, 2008
    Inventor: Don R. Sauer
  • Patent number: 6677808
    Abstract: A voltage reference circuit is arranged in a CMOS process based technology to provide a configurable voltage reference. The voltage reference includes bipolar transistors that are implemented as parasitic devices in the CMOS process. Two of the bipolar transistors are configured to generate a &Dgr;Vbe signal in the voltage reference circuit. An error amplifier cooperates with the two bipolar transistors via a control signal such that the control signal is related to &Dgr;Vbe/R. A first current source is coupled to another bipolar device, which is parallel connected to a resistor divider. The output of the resistor divider provides a divided reference signal that is related to the Vbe of the other bipolar device. Another resistor is coupled between a second current source and the output of the resistor divider such that an adjustable/temperature compensated reference signal is provided.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: January 13, 2004
    Assignee: National Semiconductor Corporation
    Inventors: S. Chen Sean, Don R. Sauer
  • Patent number: 6614293
    Abstract: A Sauer diode circuit is arranged to introduce a signal into a circuit to compensate for mismatch effects to various parameters in a current mirror circuit. Current matching between transistors is improved by providing matched errors such as forward current gain (Beta), early voltage, transconductance, channel-length modulation, as well as other sources of matching errors. The Sauer diode includes a series of transistors that are arranged to operate as a diode circuit that has errors that are matched to other components in an application circuit. Example application circuits include, but are not limited to reference circuits, operational amplifiers, comparators, analog-to-digital converters, digital-to-analog converters as well as other circuits that employ current mirror circuitry. The Sauer diode may be implemented in a single transistor technology such as MOS, BJT, FET, or a number of mixed technologies such as BiCMOS, BiFET and the like.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: September 2, 2003
    Assignee: National Semiconductor Corporation
    Inventor: Don R. Sauer
  • Patent number: 6608526
    Abstract: An output stage for an operational amplifier includes a dynamically activated CMOS drive circuit that is arranged to improve the drive characteristics of the operational amplifier. The output stage includes bipolar transistors that are arranged to clamp the signal swing at an intermediary node in the operational amplifier. The bipolar transistors activate respective portions of the CMOS drive circuit based on the signal drive at the intermediary node. The CMOS driver circuit includes a p-type field effect transistor that sources additional current into the output signal when active, and an n-type field effect transistor that sinks additional current from the output terminal when active. The output stage may include additional circuitry to ensure that parasitic capacitances associated with the gates of the p-type field effect transistor and the n-type field effect transistors are discharged at appropriate times such that power consumption is reduced and high-speed operation is enhanced.
    Type: Grant
    Filed: April 17, 2002
    Date of Patent: August 19, 2003
    Assignee: National Semiconductor Corporation
    Inventor: Don R. Sauer
  • Patent number: 6518847
    Abstract: A method and apparatus is directed to generating an oscillation frequency utilizing the thermal heat transfer properties of semiconductor material as a feedback loop in an oscillator. The oscillator includes a comparator that compares two input signals and enables one of two heater circuits. Each heater circuit is thermally coupled to a sensor and reference circuit. Each sensor and reference circuit pair is arranged such that the reference circuit is heated while the sensor cools. The combination of each sensor and reference circuit produces input signals for the comparator. The frequency of the oscillator is determined by the heat transfer rate between the heater circuit and the corresponding sensor, and the thermal cooling rate of the other sensor. Changing the biasing currents, and distances between the heat sources and the thermal sensors adjust the duty cycle and frequency.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: February 11, 2003
    Assignee: National Semiconductor Corporation
    Inventor: Don R. Sauer
  • Patent number: 6456123
    Abstract: A translation circuit for transferring a differential voltage to a ground referenced voltage includes a differential input circuit, a sample/hold (S/H) circuit, and a compensation circuit. The S/H circuit includes a S/H capacitor, a series capacitor and a switch. The S/H and series capacitors are connected in series between an output line and a source of ground potential (GROUND). The switch shorts the bottom electrode of the S/H capacitor to GROUND when executing a translation operation. The differential input circuit receives the differential voltage and selectively provides the differential voltage across the S/H capacitor so that the top and bottom electrodes of the S/H capacitor have voltages V+ and V−, respectively. Parasitic capacitance tends to add charge to the S/H capacitor during the translation operation. The compensation circuit compensates for parasitic capacitance by removing, ideally, the same amount of charge from the S/H capacitor by the end of the translation operation.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: September 24, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Dale A. Oakeson, Don R. Sauer
  • Patent number: 6433637
    Abstract: A method and apparatus is directed to a rail-to-rail MOS amplifier that operates with a very low power supply. An input stage amplifier operates over rail-to-rail common-mode voltages. The input stage amplifier includes two differential input stages that steer current to loads in a class AB turnaround stage. The class AB turnaround stage converts the differential signals into a single signal that is driven into an output stage amplifier. The output stage amplifier includes level shifting buffer amplifiers that are arranged to bias a pair of MOS output transistors. Each level shifting buffer amplifier is arranged to bias a MOS transistor in a sub-threshold operating region such that the MOS transistor operates as a resistor. The MOS resistor works in conjunction with a MOS diode to provide an AB bias voltage to a gate of a respective one of the output transistors.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: August 13, 2002
    Assignee: National Semiconductor Corporation
    Inventor: Don R. Sauer
  • Patent number: 6380723
    Abstract: A single cell voltage reference operates under low power supply requirements to provide a configurable voltage reference. The single cell voltage reference includes a diode device that is biased as a voltage source. Two series connected resistive devices are connected in parallel with the diode device. The diode is biased with a current that is proportional to delta Vbe/R, such that the impedance of the diode tracks R. Another current source that is also proportional to delta Vbe/R is provided at the junction of the two resistors such that the voltage across one of the two resistors may be employed as a reference voltage that is less than 1.2V. The ratio of the resistors and scales the reference voltage level. Voltages that are below 1.2V are provided that are temperature compensated similar to a band-gap reference. The diode voltage as driven by a current source determines the lower limit of the reference voltage.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: April 30, 2002
    Assignee: National Semiconductor Corporation
    Inventor: Don R. Sauer
  • Patent number: 6310467
    Abstract: A method and apparatus is directed to a thermal shut down for a low drop out (LDO) regulator including a MOS transistor. An error amplifier controls the gate of the MOS transistor by comparing the regulator output voltage to a reference voltage that is generated by a reference circuit. To enhance power supply rejection and improve regulation, the error amplifier and the reference circuits are powered by a potential at an internal power supply node. A power control circuit selectively couples the internal power supply node to one of the regulated output voltage and the unregulated supply voltage. A start-up circuit may be employed to ensure that regulation begins when power is applied. A temperature sensor circuit detects when the operating temperature exceeds a predetermined temperature and activates a supply transfer circuit to couple the unregulated supply to the internal power supply node.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: October 30, 2001
    Assignee: National Semiconductor Corporation
    Inventor: Don R. Sauer
  • Patent number: 6201377
    Abstract: A match-insensitive low current bias circuit uses a transistor arrangement which takes advantage of the transistors' collector current degeneration, current gain through emitter sizing, and voltage gain to minimize any errors caused by stage mismatches created during production. The bias circuit of the present invention is particularly suited to integrated circuit applications where a low biasing current is required.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: March 13, 2001
    Assignee: National Semiconductor Corp.
    Inventor: Don R. Sauer
  • Patent number: 5793242
    Abstract: An integrator circuit is disclosed which overcomes problems in the art described above. In accordance with the present invention, an integrator circuit includes a differential input transconductance stage which converts an input differential signal to a differential current at first and second internal nodes. These two internal nodes are buffered from an integrating capacitor by two pass transistors, the conductance of which is automatically adjusted in response to the voltage at the two nodes. In this manner, the first and second nodes act as nearly ideal current sources. Thus, the integrating capacitor sees a nearly infinite impedance, thereby allowing the integrator circuit to achieve a large RC time constant while employing relatively small internal resistances. Further, the integrator circuit is fully differential and includes a floating capacitor having equal leakages on each of its plates. Being responsive only to differential signals, the integrator circuit thus ignores common mode leakages.
    Type: Grant
    Filed: September 13, 1995
    Date of Patent: August 11, 1998
    Assignee: National Semiconductor Corporation
    Inventor: Don R. Sauer
  • Patent number: 5600283
    Abstract: An oscillator includes a small on-chip floating capacitor having equal parasitic leakages on each of its two plates. The oscillator is fully differential and, being responsive only to differential signals, ignores common mode parasitic leakages of the capacitor. This feature allows for a minimizing of the size of the capacitor as well as enabling the oscillator to operate on purely DC currents which, in turn, allows the output state of the oscillator to toggle without creating current spikes on the supplies. By eliminating these spikes, the oscillator does not suffer from substrate crosstalk problems and thus may be used in mixed signal applications without perturbing the operation of sensitive analog circuitry.
    Type: Grant
    Filed: September 13, 1995
    Date of Patent: February 4, 1997
    Assignee: National Semiconductor Corporation
    Inventor: Don R. Sauer
  • Patent number: 5546045
    Abstract: An integrated circuit output stage is intended for use with an operational amplifier. The output is capable of driving capacitive load to within a V.sub.SAT of the power supply rails. The complementary output transistors are driven by way of a combination of buffers and complementary differential amplifiers which act to bias the stage in class AB. The quiescent current is stabilized and controlled, in part, by simple resistor rationing. The output transistor saturation is sensed and a current limit is imposed so that hard saturation is avoided. Frequency compensation is achieved in a manner that responds to output transistor saturation so as to improve the high frequency transient response. Feedforward capacitors are also included to further improve high frequency response.
    Type: Grant
    Filed: April 19, 1995
    Date of Patent: August 13, 1996
    Assignee: National Semiconductor Corp.
    Inventor: Don R. Sauer
  • Patent number: 5525934
    Abstract: An output stage of a CMOS comparator is designed to have a limited short circuit current, while maintaining maximum output voltage swing and a low quiescent current. The output stage includes a reference voltage generation circuit, which generates a gate voltage at the output transistor of limited range, so that the short circuit current of the output transistor is limited. In one embodiment, the reference voltage is generated by a plurality of serially connected diodes.
    Type: Grant
    Filed: August 24, 1994
    Date of Patent: June 11, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Kwok-Fu Chiu, Don R. Sauer
  • Patent number: 5471175
    Abstract: An improved input protection circuit receiving a differential signal has a small signal input circuit and a large signal input circuit. The small signal input circuit is active when the differential input signal has a magnitude not exceeding a predetermined value. The large signal input circuit is active when the differential input signal has a magnitude exceeding the predetermined value. Because the small signal input circuit does not see a large differential signal across the gate terminals of its input transistors, offset voltage ("V.sub.os ") drift is avoided resulting in enhanced circuit reliability. A switch circuit isolates the small signal input circuit when the large signal input circuit is active.
    Type: Grant
    Filed: August 24, 1994
    Date of Patent: November 28, 1995
    Assignee: National Semiconductor Corporation
    Inventors: Kwok-Fu Chiu, Don R. Sauer
  • Patent number: 5471172
    Abstract: An AB Cascode amplifier provides low quiescent current operation, while maintaining the high gain and wide bandwidth of prior art folded cascode amplifier. Instead of fixed current sources, the AB cascode amplifier uses variable current sources, which are biased by a fixed small current source and two variable biased transistor.
    Type: Grant
    Filed: August 24, 1994
    Date of Patent: November 28, 1995
    Assignee: National Semiconductor Corporation
    Inventors: Kwok-Fu Chiu, Don R. Sauer
  • Patent number: 5455535
    Abstract: An interstage circuit functions to combine a first differential voltage and a second differential voltage, the first and second differential voltages being either positive or negative, to produce a current at a single ended output. A first pair of PNP transistors generates a first current corresponding to the first differential voltage, if positive, summed with a first bias current. A first pair of NPN transistors generates a second current corresponding to the second differential voltage, if positive, summed with a second bias current. A second pair of PNP transistors generates a third current corresponding to the first differential voltage, if negative, summed with the second current. A second pair of NPN transistors generates a fourth current corresponding to the second differential voltage, if negative, summed with the first current. The third current is subtracted from the fourth current to produce the current at the single ended output.
    Type: Grant
    Filed: March 3, 1994
    Date of Patent: October 3, 1995
    Assignee: National Semiconductor Corporation
    Inventor: Don R. Sauer
  • Patent number: 5414388
    Abstract: An op-amp incorporates an input stage composed of two complementary long-tailed transistor pairs driven in parallel from the input terminals. A bias supply circuit provides the tail currents which are proportioned so that the total tail current adds up to a constant sum. The bias circuit proportions the tail currents, relative to the common mode voltage, so that at least one long tailed pair will function even when the common mode is driven to the supply rail potential. The bias supply current includes cascode connected transistors to provide the tail currents and the input circuit includes active clamping transistors.
    Type: Grant
    Filed: March 3, 1994
    Date of Patent: May 9, 1995
    Assignee: National Semiconductor Corporation
    Inventor: Don R. Sauer
  • Patent number: 4550424
    Abstract: An AM stereo receiver decoder is shown. An AM detector produces the stereo L+R signal and a PM detector produces the L-R signal. The PM detector is created from a conventional FM detector that employs an input limiter driving a balanced multiplier. The limiter also drives a tuned circuit which provides quadrature drive to the multiplier. An integrator connected to the FM detector converts the response to a PM decoder. A large value inductor is simulated to appear across the integrator so as to create a low modulation frequency resonance at a subaudible frequency thereby providing a controlled pilot tone response. The inductor is simulated by the action of a first G.sub.m amplifier driving a capacitor which drives a second G.sub.m amplifier having an output coupled back to the input of the first G.sub.m amplifier. The capacitor is switched by means of a series connected switch that disconnects the capacitor when the AM exceeds a predetermined value.
    Type: Grant
    Filed: February 9, 1984
    Date of Patent: October 29, 1985
    Assignee: National Semiconductor Corporation
    Inventors: Fred T. J. Cheng, Don R. Sauer
  • Patent number: 4523156
    Abstract: A tone control circuit including an amplifier having a continuously adjustable frequency response control for varying the effect of low and high frequency filters upon the amplifier, and incorporating a novel distortion and transient suppression circuit is disclosed. A programmable variable resistance is coupled between an input and an output of said amplifier to attenuate circuit low frequency response while initially varying resistor value in response to a programming distortion/transient control signal. Thereafter, overall amplifier gain is further varied in response to the programming distortion/transient control signal by further adjusting the variable resistor value. Various embodiments of the invention provide both continuous and discrete control of tone and volume responsive to both excessive low frequency signal and transients. The present invention is implemented in both discrete and monolithic embodiments, which include both linear and CMOS technologies.
    Type: Grant
    Filed: July 25, 1983
    Date of Patent: June 11, 1985
    Assignee: National Semiconductor Corporation
    Inventor: Don R. Sauer