Abstract: An integrated circuit memory is disclosed in which an array of 8 T SRAM cells is arranged in rows and columns using a plurality of write wordlines for each row of 8 T SRAM cells to control write access to cells in the row associated with a first parity/ECC word and a second write wordline operable to control write access to cells in the row associated with a second parity/ECC word.

Abstract: In one example, an integrated circuit includes memory control logic (e.g., CMOS logic circuit) and passive variable resistance memory disposed above the memory control logic. The passive variable resistance memory, also known as resistive non-volatile memory, may be for example memristors, phase-change memory, or magnetoresistive memory. Each memory cell of the passive variable resistance memory is electrically connected to the memory control logic through at least one vertical interconnect accesses (vias). For example, the operation (e.g., write/read) of each passive variable resistance memory cell is controlled by the memory control logic. The integrated circuit may also include processor logic operatively coupled to the memory control logic.

Abstract: In one example, an integrated circuit includes memory control logic (e.g., CMOS logic circuit) on the front side of the integrated circuit die and passive variable resistance memory on the back side of the integrated circuit die. The passive variable resistance memory, also known as resistive non-volatile memory, may be for example memristors, phase-change memory, or magnetoresistive memory. Each memory cell of the passive variable resistance memory on the back side of the integrated circuit die is electrically connected to the memory control logic on the front side of the integrated circuit die through at least one through-die vertical interconnect accesses (vias). For example, the operation (e.g., write/read) of each passive variable resistance memory cell is controlled by the memory control logic. The integrated circuit may also include processor logic on the front side of the integrated circuit die operatively coupled to the memory control logic.

Abstract: In one example, an integrated circuit includes two integrated circuit dies that are face-to-face mounted together. The first integrated circuit die includes passive variable resistance memory and the second integrated circuit die includes memory control logic (e.g., CMOS logic circuit). The passive variable resistance memory, also known as resistive non-volatile memory, may be for example memristors, phase-change memory, or magnetoresistive memory. Each memory cell of the passive variable resistance memory on the first integrated circuit die is electrically connected to the memory control logic on the second integrated circuit die through at least one vertical interconnect accesses (vias). For example, the operation (e.g., write/read) of each passive variable resistance memory cell is controlled by the memory control logic. The integrated circuit may also include processor logic on the second integrated circuit die operatively coupled to the memory control logic.

Abstract: An apparatus is described comprising a signal indicative of which of a plurality of data structures stored in a queue desire to issue from the queue. The apparatus also has a content addressable memory having a plurality of cells, where each of the cells is configured to store one of the data structures. The apparatus also has an output from at least one of the cells that is indicative of whether the data structure within the at least one of the cells has issued from the queue. The apparatus also has an input to the at least one of the cells coupled to the signal.