Patents by Inventor Don Rankila
Don Rankila has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11245006Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.Type: GrantFiled: December 23, 2019Date of Patent: February 8, 2022Assignees: Polar Semiconductor, LLC, SANKEN ELECTRIC CO., LTD.Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven L. Kosier, Peter West
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Patent number: 10896885Abstract: Apparatus and associated methods relate to a bond-pad structure having small pad-substrate capacitance for use in high-voltage MOSFETs. The bond-pad structure includes upper and lower polysilicon plates interposed between a metal bonding pad and an underlying semiconductor substrate. The lower polysilicon plate is encapsulated in dielectric materials, thereby rendering it floating. The upper polysilicon plate is conductively coupled to a source of the high-voltage MOSFET. A perimeter of the metal bonding pad is substantially circumscribed, as viewed from a plan view perspective, by a perimeter of the upper polysilicon plate. A perimeter of the upper polysilicon plate is substantially circumscribed, as viewed from the plan view perspective, by a perimeter of the lower polysilicon plate. In some embodiments, the metal bonding pad is conductively coupled to a gate of the high-voltage MOSFET. The pad-substrate capacitance is advantageously made small by this bond-pad structure.Type: GrantFiled: September 13, 2017Date of Patent: January 19, 2021Assignees: Polar Semiconductor, LLC, Sanken Electric Co., Ltd.Inventors: Peter West, Dosi Dosev, Don Rankila, Tatsuya Kamimura, Steve Kosier
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Publication number: 20200127092Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.Type: ApplicationFiled: December 23, 2019Publication date: April 23, 2020Applicants: Polar Semiconductor, LLC, SANKEN ELECTRIC CO., LTD.Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven L. Kosier, Peter West
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Patent number: 10580861Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.Type: GrantFiled: February 20, 2018Date of Patent: March 3, 2020Assignees: POLAR SEMICONDUCTOR, LLC, SANKEN ELECTRIC CO., LTD.Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven Kosier, Peter West
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Patent number: 10388783Abstract: Apparatus and associate methods relate to a high-voltage MOSFET bounded by two trenches, each having dielectric sidewalls and a dielectric bottom isolating a top field plate and a bottom field plate. The top field plate is electrically connected to a biasing circuit net, and the bottom field plate is biased via a capacitive coupling to the top field plate. The upper field plate and lower field plate are configured to deplete the majority carriers in a drain region of the MOSFET bounded by the two trenches so as to equalize two local maxima of an electric field induced by a drain/body bias, the two local maxima located proximate a drain/body metallurgical junction and proximate a trench bottom. The two local maxima of the electric field are equalized by controlling a depth location of an intervening dielectric between the upper field plate and the lower field plate.Type: GrantFiled: February 17, 2016Date of Patent: August 20, 2019Assignee: Polar Semiconductor, LLCInventor: Don Rankila
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Publication number: 20190081147Abstract: Apparatus and associated methods relate to a trench Metal-Oxide-Semiconductor Field-effect Transistor (MOSFET). The trench MOSFET includes a pair of longitudinal trenches formed in a semiconductor die, thereby forming an intervening longitudinal semiconductor pillar therebetween. Each of the pair of trenches has a field plates dielectrically isolated from a conductive gate. Each of the conductive gates is dielectrically isolated from the intervening semiconductor pillar via a gate dielectric. The thickness of the gate dielectric varies along a vertical dimension of the conductive gate, thereby providing a variation in a separation distance between each conductive gate and the intervening semiconductor pillar. The separation distance decreases from a gate/source overlap region to a channel inversion region. Such a varying separation distance can advantageously improve MOSFET operating parameters.Type: ApplicationFiled: September 13, 2017Publication date: March 14, 2019Inventors: Peter West, Dosi Dosev, Don Rankila, Tatsuya Kamimura, Steve Kosier
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Publication number: 20190081016Abstract: Apparatus and associated methods relate to a bond-pad structure having small pad-substrate capacitance for use in high-voltage MOSFETs. The bond-pad structure includes upper and lower polysilicon plates interposed between a metal bonding pad and an underlying semiconductor substrate. The lower polysilicon plate is encapsulated in dielectric materials, thereby rendering it floating. The upper polysilicon plate is conductively coupled to a source of the high-voltage MOSFET. A perimeter of the metal bonding pad is substantially circumscribed, as viewed from a plan view perspective, by a perimeter of the upper polysilicon plate. A perimeter of the upper polysilicon plate is substantially circumscribed, as viewed from the plan view perspective, by a perimeter of the lower polysilicon plate. In some embodiments, the metal bonding pad is conductively coupled to a gate of the high-voltage MOSFET. The pad-substrate capacitance is advantageously made small by this bond-pad structure.Type: ApplicationFiled: September 13, 2017Publication date: March 14, 2019Inventors: Peter West, Dosi Dosev, Don Rankila, Tatsuya Kamimura, Steve Kosier
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Publication number: 20180175146Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.Type: ApplicationFiled: February 20, 2018Publication date: June 21, 2018Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven Kosier, Peter West
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Patent number: 9899343Abstract: Apparatus and associated methods relate to a bonding pad structure for a trench-based semiconductor device. The bonding pad structure reduces a peak magnitude of the electric field between a metal bonding pad and the underlying semiconductor. The bonding pad structure includes a plurality of trenches vertically extending from a top surface of a semiconductor. Each of the plurality of trenches has dielectric sidewalls and a dielectric bottom, the dielectric sidewalls and dielectric bottom electrically isolating a conductive core within each of the trenches from a region of semiconductor outside of and adjacent to each of the plurality of trenches. The bonding pad structure includes a metal bonding pad disposed above the plurality of trenches, the metal bonding pad electrically isolated from the region of semiconductor outside of the trenches. The conductive core can be biased to reduce the magnitude of the field between adjacent trenches.Type: GrantFiled: March 9, 2016Date of Patent: February 20, 2018Assignees: Polar Semiconductor, LLC, SANKEN ELECTRIC CO., LTD.Inventors: Peter West, Steven Kosier, Tatsuya Kamimura, Don Rankila
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Patent number: 9818828Abstract: Apparatus and associated methods relate to an edge-termination structure surrounding a high-voltage MOSFET for reducing a peak lateral electric field. The edge-termination structure includes a sequence of annular trenches and semiconductor pillars circumscribing the high-voltage MOSFET. Each of the annular trenches is laterally separated from the other annular trenches by one of the semiconductor pillars. Each of the annular trenches has dielectric sidewalls and a dielectric bottom electrically isolating a conductive core within each of the annular trenches from a drain-biased region of the semiconductor pillar outside of and adjacent to the annular trench. The conductive core of the innermost trench is biased, while the conductive cores of one or more outer trenches are floating. In some embodiments, a surface of an inner semiconductor pillar is biased as well. The peak lateral electric field can advantageously be reduced by physical arrangement of trenches and electrical biasing sequence.Type: GrantFiled: March 9, 2016Date of Patent: November 14, 2017Assignees: POLAR SEMICONDUCTOR, LLC, SANKEN ELECTRIC CO., LTD.Inventors: Peter West, Steven Kosier, Tatsuya Kamimura, Don Rankila
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Publication number: 20170263718Abstract: Apparatus and associated methods relate to an edge-termination structure surrounding a high-voltage MOSFET for reducing a peak lateral electric field. The edge-termination structure includes a sequence of annular trenches and semiconductor pillars circumscribing the high-voltage MOSFET. Each of the annular trenches is laterally separated from the other annular trenches by one of the semiconductor pillars. Each of the annular trenches has dielectric sidewalls and a dielectric bottom electrically isolating a conductive core within each of the annular trenches from a drain-biased region of the semiconductor pillar outside of and adjacent to the annular trench. The conductive core of the innermost trench is biased, while the conductive cores of one or more outer trenches are floating. In some embodiments, a surface of an inner semiconductor pillar is biased as well. The peak lateral electric field can advantageously be reduced by physical arrangement of trenches and electrical biasing sequence.Type: ApplicationFiled: March 9, 2016Publication date: September 14, 2017Inventors: Peter West, Steven Kosier, Tatsuya Kamimura, Don Rankila
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Publication number: 20170263580Abstract: Apparatus and associated methods relate to a bonding pad structure for a trench-based semiconductor device. The bonding pad structure reduces a peak magnitude of the electric field between a metal bonding pad and the underlying semiconductor. The bonding pad structure includes a plurality of trenches vertically extending from a top surface of a semiconductor. Each of the plurality of trenches has dielectric sidewalls and a dielectric bottom, the dielectric sidewalls and dielectric bottom electrically isolating a conductive core within each of the trenches from a region of semiconductor outside of and adjacent to each of the plurality of trenches. The bonding pad structure includes a metal bonding pad disposed above the plurality of trenches, the metal bonding pad electrically isolated from the region of semiconductor outside of the trenches. The conductive core can be biased to reduce the magnitude of the field between adjacent trenches.Type: ApplicationFiled: March 9, 2016Publication date: September 14, 2017Inventors: Peter West, Steven Kosier, Tatsuya Kamimura, Don Rankila
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Publication number: 20170236934Abstract: Apparatus and associate methods relate to a high-voltage MOSFET bounded by two trenches, each having dielectric sidewalls and a dielectric bottom isolating a top field plate and a bottom field plate. The top field plate is electrically connected to a biasing circuit net, and the bottom field plate is biased via a capacitive coupling to the top field plate. The upper field plate and lower field plate are configured to deplete the majority carriers in a drain region of the MOSFET bounded by the two trenches so as to equalize two local maxima of an electric field induced by a drain/body bias, the two local maxima located proximate a drain/body metallurgical junction and proximate a trench bottom. The two local maxima of the electric field are equalized by controlling a depth location of an intervening dielectric between the upper field plate and the lower field plate.Type: ApplicationFiled: February 17, 2016Publication date: August 17, 2017Inventor: Don Rankila
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Publication number: 20160247879Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern including a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.Type: ApplicationFiled: February 23, 2016Publication date: August 25, 2016Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven Kosier, Peter West