Abstract: A heat sink for dissipating a thermal load is disclosed that includes one or more heat sink bases configured around a central axis of the heat sink so as to define an interior space, at least one heat sink base receiving the thermal load, a thermal transport connected to the at least one heat sink base receiving the thermal load so as to distribute the thermal load in the heat sink, and heat-dissipating fins connected to each heat sink base, the heat-dissipating fins extending from each heat sink base into the interior space of the heat sink, each heat-dissipating fin shaped according to the location of the heat-dissipating fin with respect to the location of the thermal load and the location of the distributed thermal load in the heat sink.

Abstract: A heat sink for dissipating a thermal load is disclosed that includes one or more heat sink bases configured around a central axis of the heat sink so as to define an interior space, at least one heat sink base receiving the thermal load, a thermal transport connected to the at least one heat sink base receiving the thermal load so as to distribute the thermal load in the heat sink, and heat-dissipating fins connected to each heat sink base, the heat-dissipating fins extending from each heat sink base into the interior space of the heat sink, each heat-dissipating fin shaped according to the location of the heat-dissipating fin with respect to the location of the thermal load and the location of the distributed thermal load in the heat sink.

Abstract: A heat sink for dissipating a thermal load is disclosed that includes one or more heat sink bases configured around a central axis of the heat sink so as to define an interior space, at least one heat sink base receiving the thermal load, a thermal transport connected to the at least one heat sink base receiving the thermal load so as to distribute the thermal load in the heat sink, and heat-dissipating fins connected to each heat sink base, the heat-dissipating fins extending from each heat sink base into the interior space of the heat sink, each heat-dissipating fin shaped according to the location of the heat-dissipating fin with respect to the location of the thermal load and the location of the distributed thermal load in the heat sink.

Abstract: A heat sink for dissipating a thermal load is disclosed that includes one or more heat sink bases configured around a central axis of the heat sink so as to define an interior space, at least one heat sink base receiving the thermal load, a thermal transport connected to the at least one heat sink base receiving the thermal load so as to distribute the thermal load in the heat sink, and heat-dissipating fins connected to each heat sink base, the heat-dissipating fins extending from each heat sink base into the interior space of the heat sink, each heat-dissipating fin shaped according to the location of the heat-dissipating fin with respect to the location of the thermal load and the location of the distributed thermal load in the heat sink.

Abstract: A method and system utilizing backup disk drives in disk array systems. In one aspect, a disk array system includes one or more disk arrays, each including two or more disk drives. The system includes a spare disk drive, and a controller operative to assign the spare disk drive to a particular one of the disk arrays having a type different than the type of the spare disk drive in response to a failure of a disk drive of the particular disk array, such that the spare disk drive stores data from and operates in place of the failed disk drive.

Abstract: A method for supporting multiple interface standards in a connection between a computer system and a Redundant Array of Independent Disks (RAID) unit is disclosed. The method includes receiving a message indicating an initialization routine and reading a first indicator associated with a first interface standard. The method further includes loading configuration data for the first interface standard. The method further includes configuring a RAID initiator using the configuration data, if the first interface standard is identical to the actual interface standard to which the RAID unit is coupled.

Abstract: A heat sink for distributing a thermal load is disclosed that includes two or more base plates connected and oriented around a central axis of the heat sink, at least one base plate receiving the thermal load, each base plate having thermal transport paths, the thermal transport paths oriented among the base plates so as to have the capability of accepting thermal transports having a plurality of lengths for thermal distribution between at least two base plates, heat-dissipating fins connected to each base plate, the heat-dissipating fins spaced apart in parallel and extending from each base plate towards the central axis of the heat sink, and a thermal transport connected between the base plate receiving the thermal load and at least one other base plate so as to distribute the thermal load among the base plates of the heat sink.

Abstract: This invention relates to personal computers, and more particularly to a personal computer using a small computer systems interface (SCSI) controller coupled directly to the local processor bus for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. The storage controller in accordance with this invention has internal volatile memory for transitory storage of data being communicated to coupled volatile memory. It further has control drivers interposed between the internal volatile memory and external volatile memory for controlling communication of data to the external volatile memory, with an enable driver and an enable receiver enchained between the control drivers and a source of signals controlling data communication.

Abstract: This invention relates to personal computers, and more particularly to a personal computer using a small computer systems interface (SCSI) controller coupled directly to the local processor bus for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. The personal computer system has a high speed local processor data bus, at least one logical processor device coupled directly to the local processor bus and capable of signalling through the local processor bus an occurrence of the transfer of blocks of data, and a storage controller coupled directly to the local processor bus for regulating communications between the processor device and storage memory devices. The storage controller has a FIFO memory for transitory storage of blocks of data being exchanged with the local processor bus and is capable of signalling through the local processor bus the state of the FIFO memory.

Abstract: Arrangements for physically partitioning a bus having a well defined architecture as a physical entity, wherein the partitioning is logically transparent to a computer and devices which communicate through the bus and serves to avoid problems potentially arising because of the scope of actions permitted by the architecture. A typical bus architecture to which present arrangements have relevance is that associated with SCSI (Small Computer System Interface) buses. The potential problems allowed to occur architecturally involve: (a) exposures of data security/integrity; (b) excessive signal degradation due to use of signal rates which although allowed by the architecture are inappropriate for a particular bus loading environment also allowed by the architecture; (c) restrictions preventing parallel transfer of data between the computer and multiple storage devices; (d) restrictions unduly limiting the number of devices attachable to one logical bus path (one input-output channel of the computer).

Abstract: A digital bus circuit having an Address/Data port select decoder 170 in circuit communication with a Selector 194, a Data Port Buffer/Register 181, and an Address Port register 208. The Selector 194 is in circuit communication with an auto incrementor 216, an auto decrementor 218, and a polling function. The incrementor 216 serves to automatically increment an address present in the Address port register 208. The decrementor 218 serves to automatically decrement an address present in the Address port register 208. The polling function serves to reload the Address port register 208 with the same address. The present invention allows a number of enhanced programming methods which permit input and output operations to be implemented with fewer program code instructions. One of the programming methods disclosed by the present invention is an enhanced method of "polling" a device's internal register by accessing the polling function.

Abstract: This invention relates to personal computers, and more particularly to a personal computer using a small computer systems interface (SCSI) controller for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. The personal computer has three interface circuits and a controller processor. The interface circuits control exchange of data among the system central processing unit (CPU), a controller processor, and one or more storage device(s) connected to a SCSI bus. One of the interface circuits includes a least one register for storing data indicative of the content and status of a plurality of sequences of commands ("threads") issued or to be issued to the SCSI device(s).

Abstract: This invention relates to personal computers, and more particularly to a personal computer using a FIFO registers for data transfer as illustrated by a bus master device in the form of a small computer systems interface (SCSI) controller for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. In the practice of this invention, the efficiency of a system having a plurality of bus master devices is enhanced by providing for a programmable threshold fill condition for a FIFO register before arbitration for bus control occurs. Thus the invention provides an approach to maximizing the efficiency of data transfer where FIFO registers are used.

Abstract: This invention relates to personal computers and, more particularly, to a personal computer having an interface controller providing an economical way to achieve access to a direct access storage device by a small computer system interface. In accordance with this invention, the system CPU is selectively allowed to access all or only a portion of the internal registers in an interface controller, enabling implementation in conjunction with a conventional subsystem microprocessor interface to the registers if desired. With this change, either interface has full access to the interface controller's internal registers. By allowing such access, the number of component parts required can be reduced where multitasking possibilities are not desired, and the cost of providing SCSI capability significantly reduced.

Abstract: This invention relates to personal computers, and more particularly to a personal computer using a small computer systems interface (SCSI) controller coupled directly to the local processor bus for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. The personal computer has a high speed local processor data bus and a storage controller coupled directly to said local processor bus for regulating communications between a processor and storage memory devices.

Abstract: Apparatus and method for increasing efficiency of command execution from a host processor over an SCSI bus. Arbitration, selection and message out functions of SCSI protocol are implemented using a background arbitration state machine. Additional protocol functions are implemented in a foreground state machine. When the host processor issues a command for access to the SCSI bus, the background state machine can be programmed before the foreground machine completes the protocol function for a previous command. Thus, the background state machine is ready to arbitrate for access to the bus at the very next bus free condition.

Abstract: Apparatus for assigning addresses to devices connected to a small computer system interface (SCSI) bus. A second configure bus interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.

Abstract: On board diagnostic capability for a SCSI controller is provided within an adapter by providing a gate array driven by a microprocessor on board the adapter. The gate array has data and control inputs driven from the microprocessor and data and control outputs which are dot OR'ed with corresponding in/out terminals of the SCSI controller. A reset signal from a SCSI bus forms a further input to the gate array. For testing purposes the microprocessor drives the gate array inputs to simulate a fault-free or faulty device. The microprocessor detects the response of the SCSI controller to the device simulation and thereby can determine the state of health of the SCSI controller.

Abstract: In order to more effectively use read only memory space of a personal computer system, ROM code is selectively located or mapped to either an address boundary which is an even or odd integer multiple of one half the capacity of the read only memory device in which the ROM code is stored. The ROM code is stored in the read only memory device in two fields. In a first field, the ROM code is broken up into two segments, and the first segment precedes the second segment. In the second field, the same two segments are stored, but the second segment is stored preceding the first segment. A register, for storing page select bits, provides an input to an address decoder and an input to an adder, which adds unity to the contents of the register and provides its outputs to the address decoder as well. Accordingly, the address decoder will respond to either the page which is identified by the page select bits or the page following the identified page.

Abstract: Technique for dynamically maintaining alignment of servo controls in a disk drive system which uses external indicia to position the head assembly between tracks containing embedded servo signals; the latter used to control track following. Plural pairs of phase staggered track reference signals are derived from the external indicia, and during system initialization an optimal pair is selected for controlling head positioning. The system is initialized both at power up time and after detection of certain errors. The selection is made by using each pair separately to direct positioning of the head assembly over a predetermined range of sampling positions at each of which centering offsets relative to the embedded servo signals are measured and recorded in association with the respective pair. Based on an evaluation of these offsets, the system microprocessor selects a reference signal pair having the least average offset to control subsequent head positioning operations.