Patents by Inventor Don Soltis
Don Soltis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11729096Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.Type: GrantFiled: August 2, 2021Date of Patent: August 15, 2023Assignee: Intel CorporationInventors: Debendra Das Sharma, Michelle C. Jen, Mark S. Myers, Don Soltis, Ramacharan Sundararaman, Stephen R. Van Doren, Mahesh Wagh
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Publication number: 20210399982Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.Type: ApplicationFiled: August 2, 2021Publication date: December 23, 2021Inventors: Debendra Das Sharma, Michelle C. Jen, Mark S. Myers, Don Soltis, Ramacharan Sundararaman, Stephen R. Van Doren, Mahesh Wagh
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Patent number: 11095556Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.Type: GrantFiled: June 30, 2017Date of Patent: August 17, 2021Assignee: INTEL CORPORATIONInventors: Debendra Das Sharma, Michelle C. Jen, Mark S. Myers, Don Soltis, Ramacharan Sundararaman, Stephen R. Van Doren, Mahesh Wagh
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Publication number: 20190007310Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Applicant: INTEL CORPORATIONInventors: DEBENDRA DAS SHARMA, MICHELLE C. JEN, MARK S. MYERS, DON SOLTIS, RAMACHARAN SUNDARARAMAN, STEPHEN R. VAN DOREN, MAHESH WAGH
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Publication number: 20170115716Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.Type: ApplicationFiled: August 16, 2016Publication date: April 27, 2017Inventors: ANKUSH VARMA, KRISHNAKANTH V. SISTLA, MARTIN T. ROWLAND, CHRIS POIRIER, ERIC J. DEHAEMER, AVINASH N. ANANTHAKRISHNAN, JEREMY J. SHRALL, XIUTING C. MAN, STEPHEN H. GUNTHER, KRISHNA K. RANGAN, DEVADATTA V. BODAS, DON SOLTIS, HANG T. NGUYEN, CYPRIAN W. WOO, THI DANG
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Patent number: 9483293Abstract: Embodiments of a system and method for triggering an event in a hardware abstraction layer (HAL) are generally described herein. In some embodiments, the HAL can include unarchitected hardware or software that can be used to, for example, facilitate instruction emulation and debug; enable protection of model specific resources, instructions, and behaviors; redirect, resteer, or substitute instructions; and provide a framework for additional capabilities and features.Type: GrantFiled: December 30, 2011Date of Patent: November 1, 2016Assignee: Intel CorporationInventors: Cameron McNairy, Don Soltis
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Patent number: 9417681Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.Type: GrantFiled: April 27, 2015Date of Patent: August 16, 2016Assignee: Intel CorporationInventors: Ankush Varma, Krishnakanth V. Sistla, Martin T. Rowland, Chris Poirier, Eric J. Dehaemer, Avinash N. Ananthakrishnan, Jeremy J. Shrall, Xiuting C. Man, Stephen H. Gunther, Krishna K. Rangan, Devadatta V. Bodas, Don Soltis, Hang T. Nguyen, Cyprian W. Woo, Thi Dang
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Publication number: 20150241949Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.Type: ApplicationFiled: April 27, 2015Publication date: August 27, 2015Inventors: Ankush Varma, Krishnakanth V. Sistla, Martin T. Rowland, Chris Poirier, Eric J. Dehaemer, Avinash N. Ananthakrishnan, Jeremy J. Shrall, Xiuting C. Man, Stephen H. Gunther, Krishna K. Rangan, Devadatta V. Bodas, Don Soltis, Hang T. Nguyen, Cyprian W. Woo, Thi Dang
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Patent number: 9075614Abstract: A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.Type: GrantFiled: March 1, 2013Date of Patent: July 7, 2015Assignee: Intel CorporationInventors: Eric Fetzer, Reid Riedlinger, Don Soltis, William Bowhill, Satish Shrimali, Krishnakanth Sistla, Efraim Rotem, Rakesh Kumar, Vivek Garg, Alon Naveh, Lokesh Sharma
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Patent number: 9069555Abstract: A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the dynamic capacitance of the processor such that the dynamic capacitance is within an allowable dynamic capacitance value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.Type: GrantFiled: March 16, 2012Date of Patent: June 30, 2015Assignee: Intel CorporationInventors: Eric Fetzer, Reid J. Reidlinger, Don Soltis, William J. Bowhill, Satish Shrimali, Krishnakanth Sistla, Efraim Rotem, Rakesh Kumar, Vivek Garg, Alon Naveh, Lokesh Sharma
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Patent number: 9037840Abstract: An apparatus that includes a semiconductor chip having a processor and an on-die non-volatile storage resource is described. The on-die non volatile storage is to store different, appropriate performance related information for different configurations and/or usage cases of the processor for a same performance state of the processor.Type: GrantFiled: June 29, 2012Date of Patent: May 19, 2015Assignee: Intel CorporationInventors: Ankush Varma, Krishnakanth V. Sistla, Martin T. Rowland, Chris Poirier, Eric J. Dehaemer, Avinash N. Ananthakrishnan, Jeremy J. Shrall, Xiuting C. Man, Stephen H. Gunther, Krishna K. Rangan, Devadatta V. Bodas, Don Soltis, Hang T. Nguyen, Cyprian W. Woo, Thi Dang
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Publication number: 20140359640Abstract: Embodiments of a system and method for triggering an event in a hardware abstraction layer (HAL) are generally described herein. In some embodiments, the HAL can include unarchitected hardware or software that can be used to, for example, facilitate instruction emulation and debug; enable protection of model specific resources, instructions, and behaviors; redirect, resteer, or substitute instructions; and provide a framework for additional capabilities and features.Type: ApplicationFiled: December 30, 2011Publication date: December 4, 2014Inventors: Cameron McNairy, Don Soltis
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Publication number: 20140181484Abstract: According to one embodiment, a processor includes an execution pipeline for executing a plurality of threads, including a first thread and a second thread. The processor further includes a multi-thread controller (MTC) coupled to the execution pipeline to determine whether to switch threads between the first and second thread based on a thread switch policy that is selected from a list of thread switch policies based on unfairness levels of the first and second thread, and in response to determining to switch threads, to switch from executing the first thread to executing the second thread.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Inventors: James Callister, Don Soltis, Rohit Bhatia, Ramkumar Srinivasan, Steven Bostian, Richard M. Blumberg
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Publication number: 20140006761Abstract: An apparatus that includes a semiconductor chip having a processor and an on-die non-volatile storage resource is described. The on-die non volatile storage is to store different, appropriate performance related information for different configurations and/or usage cases of the processor for a same performance state of the processor.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Inventors: Ankush Varma, Krishnakanth V. Sistla, Martin T. Rowland, Chris Poirier, Eric J. Dehaemer, Avinash N. Ananthakrishnan, Jeremy J. Shrall, Xiuting C. Man, Stephen H. Gunther, Krishna K. Rangan, Devadatta V. Bodas, Don Soltis, Hang T. Nguyen, Cyprian W. Woo, Thi Dang
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Publication number: 20130232368Abstract: A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.Type: ApplicationFiled: March 1, 2013Publication date: September 5, 2013Inventors: ERIC FETZER, REID RIEDLINGER, DON SOLTIS, WILLIAM BOWHILL, SATISH SHRIMALI, KRISHNAKANTH SISTLA, EFRAIM ROTEM, RAKESH KUMAR, VIVEK GARG, ALON NAVEH, LOKESH SHARMA
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Publication number: 20120254643Abstract: A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.Type: ApplicationFiled: March 16, 2012Publication date: October 4, 2012Inventors: Eric Fetzer, Reid J. Reidlinger, Don Soltis, William J. Bowhill, Satish Shrimali, Krishnakanth Sistla, Efraim Rotem, Rakesh Kumar, Vivek Garg, Alon Naveh, Lokesh Sharma
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Publication number: 20070022273Abstract: Systems and methods for error recovery in an integer execution unit of a multi-core processor are disclosed. In an exemplary embodiment a method may comprise checking parity for a transaction in an execution data path having parallel data registers. The method may also comprise copying one of the parallel data registers to a corrupt data register if parity fails.Type: ApplicationFiled: July 19, 2005Publication date: January 25, 2007Inventors: Samuel Naffziger, Don Soltis
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Publication number: 20060259907Abstract: Systems and methods of sharing processing resources in a multi-threading environment are disclosed. An exemplary method may include allocating a lock value for a resource lock, the lock value corresponding to a state of the resource lock. A first thread may yield at least a portion of the processing resources for another thread. The resource lock may be acquired for the first thread if the lock value indicates the resource lock is available.Type: ApplicationFiled: May 10, 2005Publication date: November 16, 2006Inventors: Rohit Bhatia, Don Soltis