Patents by Inventor Don-Son Jiang
Don-Son Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230395571Abstract: An electronic package is provided, in which a first electronic element and a second electronic element are disposed on a first side of a circuit structure and a second side of the circuit structure, respectively, where a first metal layer is formed between the first side of the circuit structure and the first electronic element, a second metal layer is formed on a surface of the second electronic element, and at least one thermally conductive pillar is disposed on the second side of the circuit structure and extends into the circuit structure to thermally conduct the first metal layer and the second metal layer. Therefore, through the thermally conductive pillar, heat generated during operations of the first electronic element and the second electronic element can be quickly dissipated to an external environment and would not accumulate.Type: ApplicationFiled: August 17, 2023Publication date: December 7, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Meng-Huan Chia, Yih-Jenn Jiang, Chang-Fu Lin, Don-Son Jiang
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Publication number: 20230361091Abstract: An electronic package and a manufacturing method thereof, which embeds an electronic structure acting as an auxiliary functional component and a plurality of conductive pillars in an encapsulation layer, and disposes an electronic component on the encapsulation layer, so as to facilitate electrical transmission with the electronic component in a close range.Type: ApplicationFiled: July 11, 2023Publication date: November 9, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Wei-Jhen Chen, Chih-Hsun Hsu, Yuan-Hung Hsu, Chih-Nan Lin, Chang-Fu Lin, Don-Son Jiang, Chih-Ming Huang, Yi-Hsin Chen
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Publication number: 20230307339Abstract: An electronic package is provided, and the manufacturing method of which is to form a plurality of conductive pillars and dispose an electronic element on a first circuit structure, then cover the plurality of conductive pillars and the electronic element with a cladding layer, and then form a second circuit structure on the cladding layer, so that the plurality of conductive pillars are electrically connected to the first circuit structure and the second circuit structure, and the electronic element is electrically connected to the first circuit structure, where a fan-out redistribution layer is configured in the first circuit structure and the second circuit structure, and at least one ground layer is configured in the second circuit structure. Further, the ground layer includes a plurality of sheet bodies arranged in an array, so that at least one slot is disposed between every two adjacent sheet bodies.Type: ApplicationFiled: May 19, 2022Publication date: September 28, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Ting-Yang Chou, Yih-Jenn Jiang, Don-Son Jiang
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Patent number: 11764188Abstract: An electronic package is provided, in which a first electronic element and a second electronic element are disposed on a first side of a circuit structure and a second side of the circuit structure, respectively, where a first metal layer is formed between the first side of the circuit structure and the first electronic element, a second metal layer is formed on a surface of the second electronic element, and at least one thermally conductive pillar is disposed on the second side of the circuit structure and extends into the circuit structure to thermally conduct the first metal layer and the second metal layer. Therefore, through the thermally conductive pillar, heat generated during operations of the first electronic element and the second electronic element can be quickly dissipated to an external environment and would not accumulate.Type: GrantFiled: August 25, 2021Date of Patent: September 19, 2023Inventors: Meng-Huan Chia, Yih-Jenn Jiang, Chang-Fu Lin, Don-Son Jiang
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Patent number: 11742296Abstract: An electronic package and a manufacturing method thereof, which embeds an electronic structure acting as an auxiliary functional component and a plurality of conductive pillars in an encapsulation layer, and disposes an electronic component on the encapsulation layer, so as to facilitate electrical transmission with the electronic component in a close range.Type: GrantFiled: December 28, 2020Date of Patent: August 29, 2023Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Wei-Jhen Chen, Chih-Hsun Hsu, Yuan-Hung Hsu, Chih-Nan Lin, Chang-Fu Lin, Don-Son Jiang, Chih-Ming Huang, Yi-Hsin Chen
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Publication number: 20230268262Abstract: A method of manufacturing an electronic package is provided and includes disposing a circuit member and a plurality of electronic elements on opposite sides of a carrier structure having circuit layers respectively, so that any two of the plurality of electronic elements can be electrically connected to each other via the circuit layers and the circuit member, where a vertical projected area of the carrier structure is larger than a vertical projected area of the circuit member, such that the circuit member is free from being protruded from side surfaces of the carrier structure. Therefore, the circuit member replaces a part of circuit layers of the carrier structure to reduce the difficulty of fabricating the circuit layers in the carrier structure.Type: ApplicationFiled: May 23, 2022Publication date: August 24, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Li-Chu Chang, Yuan-Hung Hsu, Don-Son Jiang
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Publication number: 20230187382Abstract: An electronic package is provided and includes at least one protective structure positioned between a first electronic element and a second electronic element on a carrier for reducing stresses generated inside the first electronic element and the second electronic element when a filling material is formed on the carrier, encapsulates the protective structure and comes into contact with the first electronic element and the second electronic element, thereby preventing cracking of the first electronic element and the second electronic element and improving the reliability of the electronic package.Type: ApplicationFiled: February 13, 2023Publication date: June 15, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chih-Hsun Hsu, Chi-Jen Chen, Hsi-Chang Hsu, Yuan-Hung Hsu, Rui-Feng Tai, Don-Son Jiang
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Patent number: 11610850Abstract: An electronic package is provided and includes at least one protective structure positioned between a first electronic element and a second electronic element on a carrier for reducing stresses generated inside the first electronic element and the second electronic element when a filling material is formed on the carrier, encapsulates the protective structure and comes into contact with the first electronic element and the second electronic element, thereby preventing cracking of the first electronic element and the second electronic element and improving the reliability of the electronic package.Type: GrantFiled: January 28, 2021Date of Patent: March 21, 2023Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chih-Hsun Hsu, Chi-Jen Chen, Hsi-Chang Hsu, Yuan-Hung Hsu, Rui-Feng Tai, Don-Son Jiang
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Publication number: 20230015721Abstract: An electronic package is provided, in which a first electronic element and a second electronic element are disposed on a first side of a circuit structure and a second side of the circuit structure, respectively, where a first metal layer is formed between the first side of the circuit structure and the first electronic element, a second metal layer is formed on a surface of the second electronic element, and at least one thermally conductive pillar is disposed on the second side of the circuit structure and extends into the circuit structure to thermally conduct the first metal layer and the second metal layer. Therefore, through the thermally conductive pillar, heat generated during operations of the first electronic element and the second electronic element can be quickly dissipated to an external environment and would not accumulate.Type: ApplicationFiled: August 25, 2021Publication date: January 19, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Meng-Huan Chia, Yih-Jenn Jiang, Chang-Fu Lin, Don-Son Jiang
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Patent number: 11532528Abstract: An electronic package and a method for manufacturing the electronic package are provided. The method includes forming a slope surface on at least one side surface of at least one of a plurality of electronic components, and then disposing the plurality of electronic components on a carrier structure, such that the two adjacent electronic components form a space by the slope surface. Afterwards, an encapsulation layer is formed on the carrier structure and filled into the space to cover the two adjacent electronic components so as to disperse stress on the electronic components through the design of the space to prevent cracking due to stress concentration.Type: GrantFiled: January 28, 2021Date of Patent: December 20, 2022Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chi-Jen Chen, Hsi-Chang Hsu, Yuan-Hung Hsu, Chang-Fu Lin, Don-Son Jiang
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Publication number: 20220392861Abstract: An electronic package is provided and includes a carrier for carrying electronic components. Electrical contact pads of the carrier for planting solder balls are connected with a plurality of columnar conductors, and the conductors are electrically connected to a circuit portion in the carrier. By connecting a plurality of conductors with a single electrical contact pad, structural stress can be distributed and breakage of the circuit portion can be prevented.Type: ApplicationFiled: July 7, 2021Publication date: December 8, 2022Applicant: SILICONWARE PRECISION INDUST RIES CO., LT D.Inventors: Chi-Ren Chen, Po-Yung Chang, Pei-Geng Weng, Yuan-Hung Hsu, Chang-Fu Lin, Don-Son Jiang
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Patent number: 11398429Abstract: An electronic package is provided, which is disposed with a second electronic component and a third electronic component on a first electronic component as a carrier structure, such that there is no need to match a layout size of the conventional package substrate. Therefore, the first electronic component can be designed as a System on a Chip (SoC) with a smaller size to improve the process yield.Type: GrantFiled: December 1, 2020Date of Patent: July 26, 2022Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Cheng Kai Chang, Chang-Fu Lin, Don-Son Jiang
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Publication number: 20220189900Abstract: An electronic package is provided and includes at least one conductor with a relatively large width formed on an electrode pad of an electronic element and in contact with a circuit layer. As such, when the electronic element and the circuit layer deviate in position relative to one another, the circuit layer will be still in contact with the conductor and hence electrically connected to the electronic element.Type: ApplicationFiled: February 9, 2021Publication date: June 16, 2022Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chia-Yu Kuo, Rui-Feng Tai, Yih-Jenn Jiang, Don-Son Jiang, Chang-Fu Lin
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Publication number: 20220181225Abstract: An electronic package and a method for manufacturing the electronic package are provided. The method includes forming a slope surface on at least one side surface of at least one of a plurality of electronic components, and then disposing the plurality of electronic components on a carrier structure, such that the two adjacent electronic components form a space by the slope surface. Afterwards, an encapsulation layer is formed on the carrier structure and filled into the space to cover the two adjacent electronic components so as to disperse stress on the electronic components through the design of the space to prevent cracking due to stress concentration.Type: ApplicationFiled: January 28, 2021Publication date: June 9, 2022Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chi-Jen Chen, Hsi-Chang Hsu, Yuan-Hung Hsu, Chang-Fu Lin, Don-Son Jiang
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Publication number: 20220173052Abstract: An electronic package is provided and includes at least one protective structure positioned between a first electronic element and a second electronic element on a carrier for reducing stresses generated inside the first electronic element and the second electronic element when a filling material is formed on the carrier, encapsulates the protective structure and comes into contact with the first electronic element and the second electronic element, thereby preventing cracking of the first electronic element and the second electronic element and improving the reliability of the electronic package.Type: ApplicationFiled: January 28, 2021Publication date: June 2, 2022Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chih-Hsun Hsu, Chi-Jen Chen, Hsi-Chang Hsu, Yuan-Hung Hsu, Rui-Feng Tai, Don-Son Jiang
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Publication number: 20220148975Abstract: An electronic package and a manufacturing method thereof, which embeds an electronic structure acting as an auxiliary functional component and a plurality of conductive pillars in an encapsulation layer, and disposes an electronic component on the encapsulation layer, so as to facilitate electrical transmission with the electronic component in a close range.Type: ApplicationFiled: December 28, 2020Publication date: May 12, 2022Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Wei-Jhen Chen, Chih-Hsun Hsu, Yuan-Hung Hsu, Chih-Nan Lin, Chang-Fu Lin, Don-Son Jiang, Chih-Ming Huang, Yi-Hsin Chen
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Publication number: 20220093518Abstract: An electronic package is provided, which is disposed with a second electronic component and a third electronic component on a first electronic component as a carrier structure, such that there is no need to match a layout size of the conventional package substrate. Therefore, the first electronic component can be designed as a System on a Chip (SoC) with a smaller size to improve the process yield.Type: ApplicationFiled: December 1, 2020Publication date: March 24, 2022Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Cheng Kai Chang, Chang-Fu Lin, Don-Son Jiang
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Publication number: 20200328142Abstract: A package stack structure and a method for fabricating the same are provided. An electronic component is disposed on the topmost one of a plurality of organic material substrates, and no chip is disposed on the remaining organic material substrates. A predefined layer number of circuit layers are disposed in the organic material substrates, and distributes the thermal stress via the organic material substrates. Therefore, the bottommost one of the organic material substrates will not be separated from a circuit board due to CTE mismatch. Also a carrier component is provided.Type: ApplicationFiled: August 12, 2019Publication date: October 15, 2020Inventors: Don-Son Jiang, Nai-Hao Kao, Chih-Sheng Lin, Szu-Hsien Chen, Chih-Yuan Shih, Chia-Cheng Chen, Yu-Cheng Pai, Hsuan-Hao Mi
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Patent number: 10163662Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.Type: GrantFiled: April 4, 2017Date of Patent: December 25, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Cheng-Chia Chiang, Don-Son Jiang, Lung-Yuan Wang, Shih-Hao Tung, Shu-Huei Huang
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Patent number: 10115712Abstract: An electronic module is provided, which includes a first package and a second package stacked on the first package. The first package has an encapsulant and an electronic element embedded in the encapsulant. The second package has an insulating layer and an antenna structure formed on and extending through the insulating layer. The insulating layer is bonded to the encapsulant with the antenna structure being electrically connected to the electronic element. Since the second package having the antenna structure is stacked on the first package, the invention eliminates the need to increase the area of the first package for mounting the antenna structure and hence allows the electronic module to meet the miniaturization requirement.Type: GrantFiled: December 24, 2015Date of Patent: October 30, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Shao-Chueh Hu, Yueh-Chiung Chang, Don-Son Jiang