Patents by Inventor Don-Son Jiang

Don-Son Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11398429
    Abstract: An electronic package is provided, which is disposed with a second electronic component and a third electronic component on a first electronic component as a carrier structure, such that there is no need to match a layout size of the conventional package substrate. Therefore, the first electronic component can be designed as a System on a Chip (SoC) with a smaller size to improve the process yield.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: July 26, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Cheng Kai Chang, Chang-Fu Lin, Don-Son Jiang
  • Publication number: 20220189900
    Abstract: An electronic package is provided and includes at least one conductor with a relatively large width formed on an electrode pad of an electronic element and in contact with a circuit layer. As such, when the electronic element and the circuit layer deviate in position relative to one another, the circuit layer will be still in contact with the conductor and hence electrically connected to the electronic element.
    Type: Application
    Filed: February 9, 2021
    Publication date: June 16, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chia-Yu Kuo, Rui-Feng Tai, Yih-Jenn Jiang, Don-Son Jiang, Chang-Fu Lin
  • Publication number: 20220181225
    Abstract: An electronic package and a method for manufacturing the electronic package are provided. The method includes forming a slope surface on at least one side surface of at least one of a plurality of electronic components, and then disposing the plurality of electronic components on a carrier structure, such that the two adjacent electronic components form a space by the slope surface. Afterwards, an encapsulation layer is formed on the carrier structure and filled into the space to cover the two adjacent electronic components so as to disperse stress on the electronic components through the design of the space to prevent cracking due to stress concentration.
    Type: Application
    Filed: January 28, 2021
    Publication date: June 9, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Jen Chen, Hsi-Chang Hsu, Yuan-Hung Hsu, Chang-Fu Lin, Don-Son Jiang
  • Publication number: 20220173052
    Abstract: An electronic package is provided and includes at least one protective structure positioned between a first electronic element and a second electronic element on a carrier for reducing stresses generated inside the first electronic element and the second electronic element when a filling material is formed on the carrier, encapsulates the protective structure and comes into contact with the first electronic element and the second electronic element, thereby preventing cracking of the first electronic element and the second electronic element and improving the reliability of the electronic package.
    Type: Application
    Filed: January 28, 2021
    Publication date: June 2, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsun Hsu, Chi-Jen Chen, Hsi-Chang Hsu, Yuan-Hung Hsu, Rui-Feng Tai, Don-Son Jiang
  • Publication number: 20220148975
    Abstract: An electronic package and a manufacturing method thereof, which embeds an electronic structure acting as an auxiliary functional component and a plurality of conductive pillars in an encapsulation layer, and disposes an electronic component on the encapsulation layer, so as to facilitate electrical transmission with the electronic component in a close range.
    Type: Application
    Filed: December 28, 2020
    Publication date: May 12, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Wei-Jhen Chen, Chih-Hsun Hsu, Yuan-Hung Hsu, Chih-Nan Lin, Chang-Fu Lin, Don-Son Jiang, Chih-Ming Huang, Yi-Hsin Chen
  • Publication number: 20220093518
    Abstract: An electronic package is provided, which is disposed with a second electronic component and a third electronic component on a first electronic component as a carrier structure, such that there is no need to match a layout size of the conventional package substrate. Therefore, the first electronic component can be designed as a System on a Chip (SoC) with a smaller size to improve the process yield.
    Type: Application
    Filed: December 1, 2020
    Publication date: March 24, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Cheng Kai Chang, Chang-Fu Lin, Don-Son Jiang
  • Publication number: 20200328142
    Abstract: A package stack structure and a method for fabricating the same are provided. An electronic component is disposed on the topmost one of a plurality of organic material substrates, and no chip is disposed on the remaining organic material substrates. A predefined layer number of circuit layers are disposed in the organic material substrates, and distributes the thermal stress via the organic material substrates. Therefore, the bottommost one of the organic material substrates will not be separated from a circuit board due to CTE mismatch. Also a carrier component is provided.
    Type: Application
    Filed: August 12, 2019
    Publication date: October 15, 2020
    Inventors: Don-Son Jiang, Nai-Hao Kao, Chih-Sheng Lin, Szu-Hsien Chen, Chih-Yuan Shih, Chia-Cheng Chen, Yu-Cheng Pai, Hsuan-Hao Mi
  • Patent number: 10163662
    Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: December 25, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-Chia Chiang, Don-Son Jiang, Lung-Yuan Wang, Shih-Hao Tung, Shu-Huei Huang
  • Patent number: 10115712
    Abstract: An electronic module is provided, which includes a first package and a second package stacked on the first package. The first package has an encapsulant and an electronic element embedded in the encapsulant. The second package has an insulating layer and an antenna structure formed on and extending through the insulating layer. The insulating layer is bonded to the encapsulant with the antenna structure being electrically connected to the electronic element. Since the second package having the antenna structure is stacked on the first package, the invention eliminates the need to increase the area of the first package for mounting the antenna structure and hence allows the electronic module to meet the miniaturization requirement.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: October 30, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shao-Chueh Hu, Yueh-Chiung Chang, Don-Son Jiang
  • Publication number: 20170207104
    Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.
    Type: Application
    Filed: April 4, 2017
    Publication date: July 20, 2017
    Inventors: Cheng-Chia Chiang, Don-Son Jiang, Lung-Yuan Wang, Shih-Hao Tung, Shu-Huei Huang
  • Patent number: 9673140
    Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a laminate on the carrier, wherein the laminate has a built-up portion and a release portion smaller in size than the built-up portion, the release portion covering the bonding pads and the built-up portion being laminated on the release portion and the carrier; forming a plurality of conductive posts in the built-up portion; and removing the release portion and the built-up portion on the release portion such that a cavity is formed in the laminate to expose the bonding pads, the conductive posts being positioned around a periphery of the cavity. Therefore, the present invention has simplified processes.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: June 6, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chia-Cheng Chen, Ming-Chen Sun, Tzu-Chieh Shen, Shih-Chao Chiu, Wei-Chung Hsiao, Yu-Cheng Pai, Don-Son Jiang
  • Patent number: 9646921
    Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: May 9, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-Chia Chiang, Don-Son Jiang, Lung-Yuan Wang, Shih-Hao Tung, Shu-Huei Huang
  • Publication number: 20170048981
    Abstract: An electronic module is provided, which includes a first package and a second package stacked on the first package. The first package has an encapsulant and an electronic element embedded in the encapsulant. The second package has an insulating layer and an antenna structure formed on and extending through the insulating layer. The insulating layer is bonded to the encapsulant with the antenna structure being electrically connected to the electronic element. Since the second package having the antenna structure is stacked on the first package, the invention eliminates the need to increase the area of the first package for mounting the antenna structure and hence allows the electronic module to meet the miniaturization requirement.
    Type: Application
    Filed: December 24, 2015
    Publication date: February 16, 2017
    Inventors: Shao-Chueh Hu, Yueh-Chiung Chang, Don-Son Jiang
  • Publication number: 20150287671
    Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a laminate on the carrier, wherein the laminate has a built-up portion and a release portion smaller in size than the built-up portion, the release portion covering the bonding pads and the built-up portion being laminated on the release portion and the carrier; forming a plurality of conductive posts in the built-up portion; and removing the release portion and the built-up portion on the release portion such that a cavity is formed in the laminate to expose the bonding pads, the conductive posts being positioned around a periphery of the cavity. Therefore, the present invention has simplified processes.
    Type: Application
    Filed: February 12, 2015
    Publication date: October 8, 2015
    Inventors: Chia-Cheng Chen, Ming-Chen Sun, Tzu-Chieh Shen, Shih-Chao Chiu, Wei-Chung Hsiao, Yu-Cheng Pai, Don-Son Jiang
  • Publication number: 20150187722
    Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.
    Type: Application
    Filed: April 17, 2014
    Publication date: July 2, 2015
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Cheng-Chia Chiang, Don-Son Jiang, Lung-Yuan Wang, Shih-Hao Tung, Shu-Huei Huang
  • Publication number: 20150102484
    Abstract: A package structure is disclosed, which includes: a first substrate; a build-up layer formed on and electrically connected to the first substrate and having a cavity; at least an electronic element disposed in the cavity and electrically connected to the first substrate; a stack member disposed on the build-up layer so as to be stacked on the first substrate; and an encapsulant formed between the build-up layer and the stack member. The build-up layer facilitates to achieve a stand-off effect and prevent solder bridging.
    Type: Application
    Filed: December 20, 2013
    Publication date: April 16, 2015
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD
    Inventors: Chia-Cheng Chen, Ming-Chen Sun, Tzu-Chieh Shen, Liang-yi Hung, Wei-chung Hsiao, Yu-cheng Pai, Shih-Chao Chiu, Don-Son Jiang, Yi-Feng Chang, Lung-Yuan Wang
  • Patent number: 8304665
    Abstract: A package substrate having landless conductive traces is proposed, which includes a core layer with a plurality of plated through holes formed therein, and a plurality of conductive traces formed on at least a surface of the core layer. Each of the conductive traces has a connection end, a bond pad end, and a base body connecting the connection end and the bond pad end, the conductive trace is electrically connected to a corresponding one of the plated through holes through the connection end, and the connection end has a width greater than that of the base body but not greater than the diameter of the plated through hole, thereby increasing the contact area between the conductive trace and the plated through hole and preventing the contact surface of the conductive trace with the plated through hole from cracking.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: November 6, 2012
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chiang-Cheng Chang, Yen-Ping Wang, Don-Son Jiang, Jeng-Yuan Lai, Yu-Po Wang
  • Publication number: 20090283303
    Abstract: A package substrate having landless conductive traces is proposed, which includes a core layer with a plurality of plated through holes formed therein, and a plurality of conductive traces formed on at least a surface of the core layer. Each of the conductive traces has a connection end, a bond pad end, and a base body connecting the connection end and the bond pad end, the conductive trace is electrically connected to a corresponding one of the plated through holes through the connection end, and the connection end has a width greater than that of the base body but not greater than the diameter of the plated through hole, thereby increasing the contact area between the conductive trace and the plated through hole and preventing the contact surface of the conductive trace with the plated through hole from cracking.
    Type: Application
    Filed: November 7, 2008
    Publication date: November 19, 2009
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chiang-Cheng Chang, Yen-Ping Wang, Don-Son Jiang, Jeng-Yuan Lai, Yu-Po Wang