Patents by Inventor Don Templeton
Don Templeton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11941490Abstract: Techniques regarding quantum computer error mitigation are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an error mitigation component that interpolates a gate parameter associated with a target stretch factor from a reference model that includes reference gate parameters for a quantum gate calibrated at a plurality of reference stretch factors.Type: GrantFiled: February 22, 2022Date of Patent: March 26, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel Josef Egger, Don Greenberg, Douglas Templeton McClure, III, Sarah Elizabeth Sheldon, Youngseok Kim
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Patent number: 11495568Abstract: An IC package including an integrated circuit die having a major surface and one or more solder bumps located on the major surface in at least one corner region of the major surface and a substrate having a surface, the surface including bump pads thereon. The major surface of the integrated circuit die faces the substrate surface, the one or more solder bumps are bonded to individual ones of the bump pads to thereby form a bond joint, the major surface of the integrated circuit die has a footprint area of at least about 400 mm2. A ratio of a coefficient of thermal expansion of the substrate (CTEsub) to a coefficient of thermal expansion of the integrated circuit die (CTEdie) is at least about 3:1. A method of manufacturing an IC package is also disclosed.Type: GrantFiled: January 22, 2021Date of Patent: November 8, 2022Assignee: NVIDIA CorporationInventors: Jayprakash Chipalkatti, Zuhair Bokharey, Don Templeton, Brian Schieck, Julie Lam, Prashant Pathak
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Publication number: 20210151403Abstract: An IC package including an integrated circuit die having a major surface and one or more solder bumps located on the major surface in at least one corner region of the major surface and a substrate having a surface, the surface including bump pads thereon. The major surface of the integrated circuit die faces the substrate surface, the one or more solder bumps are bonded to individual ones of the bump pads to thereby form a bond joint, the major surface of the integrated circuit die has a footprint area of at least about 400 mm2. A ratio of a coefficient of thermal expansion of the substrate (CTEsub) to a coefficient of thermal expansion of the integrated circuit die (CTEdie) is at least about 3:1. A method of manufacturing an IC package is also disclosed.Type: ApplicationFiled: January 22, 2021Publication date: May 20, 2021Inventors: Jayprakash Chipalkatti, Zuhair Bokharey, Don Templeton, Brian Schieck, Julie Lam, Prashant Pathak
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Patent number: 10957651Abstract: A die package is disclosed through which power domains within the chip may be isolated by removing vias within the package substrate, rather than power gating. Multiple substrate options may be configured without specific vias. This eliminates the need to design power gating circuitry into the die, freeing up that die area for more functional logic. The solution allows the die package to retain the same pinout for use by PCB designers, regardless of which power domains are gated.Type: GrantFiled: August 7, 2019Date of Patent: March 23, 2021Assignee: NVIDIA Corp.Inventors: Don Templeton, Luke Young Chang, Narayan Kulshrestha
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Patent number: 10943882Abstract: An IC package including an integrated circuit die having a major surface and one or more solder bumps located on the major surface in at least one corner region of the major surface and a substrate having a surface, the surface including bump pads thereon. The major surface of the integrated circuit die faces the substrate surface, the one or more solder bumps are bonded to individual ones of the bump pads to thereby form a bond joint, the major surface of the integrated circuit die has a footprint area of at least about 400 mm2. A ratio of a coefficient of thermal expansion of the substrate (CTEsub) to a coefficient of thermal expansion of the integrated circuit die (CTEdie) is at least about 3:1. A method of manufacturing an IC package is also disclosed.Type: GrantFiled: August 28, 2019Date of Patent: March 9, 2021Assignee: Nvidia CorporationInventors: Jayprakash Chipalkatti, Zuhair Bokharey, Don Templeton, Brian Schieck, Julie Lam, Prashant Pathak
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Publication number: 20210066227Abstract: An IC package including an integrated circuit die having a major surface and one or more solder bumps located on the major surface in at least one corner region of the major surface and a substrate having a surface, the surface including bump pads thereon. The major surface of the integrated circuit die faces the substrate surface, the one or more solder bumps are bonded to individual ones of the bump pads to thereby form a bond joint, the major surface of the integrated circuit die has a footprint area of at least about 400 mm2. A ratio of a coefficient of thermal expansion of the substrate (CTEsub) to a coefficient of thermal expansion of the integrated circuit die (CTEdie) is at least about 3:1. A method of manufacturing an IC package is also disclosed.Type: ApplicationFiled: August 28, 2019Publication date: March 4, 2021Inventors: Jayprakash Chipalkatti, Zuhair Bokharey, Don Templeton, Brian Schieck, Julie Lam, Prashant Pathak
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Publication number: 20210043574Abstract: A die package is disclosed through which power domains within the chip may be isolated by removing vias within the package substrate, rather than power gating. Multiple substrate options may be configured without specific vias. This eliminates the need to design power gating circuitry into the die, freeing up that die area for more functional logic. The solution allows the die package to retain the same pinout for use by PCB designers, regardless of which power domains are gated.Type: ApplicationFiled: August 7, 2019Publication date: February 11, 2021Applicant: NVIDIA Corp.Inventors: Don Templeton, Luke Young Chang, Narayan Kulshrestha
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Patent number: 10685925Abstract: Systems and methods that facilitate resistance and capacitance balancing are presented. In one embodiment, a system comprises: a plurality of ground lines configured to ground components; and a plurality of signal bus lines interleaved with the plurality of ground lines, wherein the interleaving is configured so that plurality of signal bus lines and plurality of ground lines are substantially evenly spaced and the plurality of signal bus lines convey a respective plurality of signals have similar resistance and capacitance constants that are balanced. The plurality of signals can see a substantially equal amount ground surface and have similar amounts of capacitance. The plurality of signal bus lines can have similar cross sections and lengths with similar resistances. The plurality of signal bus lines interleaved with the plurality of ground lines can be included in a two copper layer interposer design with one redistribution layer (RDL).Type: GrantFiled: January 26, 2018Date of Patent: June 16, 2020Assignee: NVIDIA CORPORATIONInventors: Jim Dobbins, Sheetal Jain, Don Templeton, Yaping Zhou, Wenjun Shi, Sunil Sudhakaran
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Patent number: 10600730Abstract: In one embodiment, a system comprises: a plurality of aggressor bus lines; and a plurality of differential pair bus lines that are located in relatively parallel close proximity to the plurality of aggressor bus lines, wherein at least two of the plurality of differential pair bus lines change location with respect to each other at a point that has a cancelling affect on cross talk from the plurality of aggressor bus lines, wherein the change includes cross over routing. The plurality of differential pair bus lines can convey differential clock signals. The routing of the plurality of differential pair bus lines is substantially parallel to one another before and after the change.Type: GrantFiled: January 26, 2018Date of Patent: March 24, 2020Assignee: NVIDIA CORPORATIONInventors: Jim Dobbins, Sheetal Jain, Don Templeton, Yaping Zhou, Wenjun Shi, Sunil Sudhakaran
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Publication number: 20190237399Abstract: In one embodiment, a system comprises: a plurality of aggressor bus lines; and a plurality of differential pair bus lines that are located in relatively parallel close proximity to the plurality of aggressor bus lines, wherein at least two of the plurality of differential pair bus lines change location with respect to each other at a point that has a cancelling affect on cross talk from the plurality of aggressor bus lines, wherein the change includes cross over routing. The plurality of differential pair bus lines can convey differential clock signals. The routing of the plurality of differential pair bus lines is substantially parallel to one another before and after the change.Type: ApplicationFiled: January 26, 2018Publication date: August 1, 2019Inventors: Jim Dobbins, Sheetal Jain, Don Templeton, Yaping Zhou, Wenjun Shi, Sunil Sudhakaran
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Publication number: 20190237417Abstract: Systems and methods that facilitate resistance and capacitance balancing are presented. In one embodiment, a system comprises: a plurality of ground lines configured to ground components; and a plurality of signal bus lines interleaved with the plurality of ground lines, wherein the interleaving is configured so that plurality of signal bus lines and plurality of ground lines are substantially evenly spaced and the plurality of signal bus lines convey a respective plurality of signals have similar resistance and capacitance constants that are balanced. The plurality of signals can see a substantially equal amount ground surface and have similar amounts of capacitance. The plurality of signal bus lines can have similar cross sections and lengths with similar resistances. The plurality of signal bus lines interleaved with the plurality of ground lines can be included in a two copper layer interposer design with one redistribution layer (RDL).Type: ApplicationFiled: January 26, 2018Publication date: August 1, 2019Inventors: Jim Dobbins, Sheetal Jain, Don Templeton, Yaping Zhou, Wenjun Shi, Sunil Sudhakaran