Patents by Inventor Don W. Jillie

Don W. Jillie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4808259
    Abstract: A method for etching of metal-oxide-semiconductor (MOS) devices utilizing a multi-step power reduction plasma etching recipe to reduce ion bombardment damage on the resulting surface. The multi-step power reduction recipe allows for reasonable throughput of wafers due to a relatively high etch rate at the upper layers of the surface followed by progressively lower power corresponding lower etch rates at the lower levels of the surface. The etching process is followed by a cleaning process to remove metallic contamination resulting from the plasma etching process to yield an excellent surface for growing low defect density MOS gate oxides with high dielectric integrity.
    Type: Grant
    Filed: January 25, 1988
    Date of Patent: February 28, 1989
    Assignee: Intel Corporation
    Inventors: Don W. Jillie, Jr., Gerald Yin, Glen Wada
  • Patent number: 4554567
    Abstract: Superconductive integrated logic gate circuits of the magnetically controlled type incorporating Josephson tunnel junctions utilize a superconductive layer that forms a base electrode for Josephson junction devices on the integrated circuit, a ground plane, and magnetic control lines. A layer of super-conductive material superposed on a barrier layer provides inductive loops connected to junction counterelectrodes and coupled to the magnetic control lines. By patterning the control lines in the same plane as the ground plane-base electrode layer, two layers, an insulating layer and a super-conductive layer, can be eliminated from the prior art structure of a 1:2:1 magnetically controlled logic gate interferometer. A preferred embodiment utilizing an all refractory superconductor-barrier-superconductor trilayer patterned by local anodization is also described. Processes for manufacturing the embodiments of the invention are disclosed.
    Type: Grant
    Filed: March 21, 1983
    Date of Patent: November 19, 1985
    Assignee: Sperry Corporation
    Inventors: Don W. Jillie, Lawrence N. Smith
  • Patent number: 4536414
    Abstract: A superconductive tunnel junction device comprises first and second superconductive electrodes with a barrier disposed therebetween where the first superconductive electrode and the barrier are formed without interruption in the same vacuum system pump down and with the first superconductive electrode subjected to sputter etching in an argon plasma before the deposition of the barrier for improving the characteristics of the device.
    Type: Grant
    Filed: January 17, 1983
    Date of Patent: August 20, 1985
    Assignee: Sperry Corporation
    Inventors: Harry Kroger, Don W. Jillie, Lawrence N. Smith
  • Patent number: 4498228
    Abstract: Josephson junction integrated circuits of the current injection type and magnetically controlled type utilize a superconductive layer that forms both Josephson junction electrode for the Josephson junction devices on the integrated circuit as well as a ground plane for the integrated circuit. Large area Josephson junctions are utilized for effecting contact to lower superconductive layers and islands are formed in superconductive layers to provide isolation between the groundplane function and the Josephson junction electrode function as well as to effect crossovers. A superconductor-barrier-superconductor trilayer patterned by local anodization is also utilized with additional layers formed thereover. Methods of manufacturing the embodiments of the invention are disclosed.
    Type: Grant
    Filed: November 14, 1983
    Date of Patent: February 12, 1985
    Assignee: Sperry Corporation
    Inventors: Don W. Jillie, Jr., Lawrence N. Smith
  • Patent number: 4430662
    Abstract: Josephson junction integrated circuits of the current injection type and magnetically controlled type utilize a superconductive layer that forms both Josephson junction electrode for the Josephson junction devices on the integrated circuit as well as a ground plane for the integrated circuit. Large area Josephson junctions are utilized for effecting contact to lower superconductive layers and islands are formed in superconductive layers to provide isolation between the groundplane function and the Josephson junction electrode function as well as to effect crossovers. A superconductor-barrier-superconductor trilayer patterned by local anodization is also utilized with additional layers formed thereover. Methods of manufacturing the embodiments of the invention are disclosed.
    Type: Grant
    Filed: April 9, 1981
    Date of Patent: February 7, 1984
    Assignee: Sperry Corporation
    Inventors: Don W. Jillie, Jr., Lawrence N. Smith
  • Patent number: 4263603
    Abstract: A process for forming subminiature bores through very thin layers of insulative material disposed between spaced electrical conductors permits the lining of the conductors by a further conductor of microscopic cross section whose dimensions are readily controlled. The method provides reliable reproduction of weak link conductors for employment in applications such as Josephson superconductive devices.
    Type: Grant
    Filed: June 6, 1979
    Date of Patent: April 21, 1981
    Assignee: Sperry Corporation
    Inventor: Don W. Jillie, Jr.
  • Patent number: 4177476
    Abstract: The disclosed SQUID (Superconducting Quantum Interference Device) comprises two superposed superconductive layers with an insulating layer therebetween. A plurality of holes through the insulating layer filled with non-superconductive material form weak-links between the superconductive layers by the superconductive proximity effect. One or more control lines superposed with respect to the superconductive layers provide magnetic flux through the area between the weak-links to control the zero voltage supercurrent flowing through the weak-links from one of the superconductive layers to the other thereby providing the switching function for Josephson superconductive circuits. The non-superconductive material forming the weak-links in the holes provides, inter alia, favorable impedance characteristics for the device.
    Type: Grant
    Filed: May 5, 1978
    Date of Patent: December 4, 1979
    Assignee: Sperry Rand Corporation
    Inventors: Harry Kroger, Don W. Jillie, Jr.
  • Patent number: 4176029
    Abstract: A process for forming subminiature bores through very thin layers of insulative material disposed between spaced electrical conductors permits the joining of the conductors by a further conductor of microscopic cross section whose dimensions are readily controlled. The method provides reliable reproduction of weak link conductors for employment in applications such as Josephson superconductive devices.
    Type: Grant
    Filed: March 2, 1978
    Date of Patent: November 27, 1979
    Assignee: Sperry Rand Corporation
    Inventor: Don W. Jillie, Jr.