Abstract: A high-speed flip-flop is provided that implements a low power consumption and a high-speed response caused by an interior capacitance reduction. A D flip-flop includes a first latch that receives a clock signal and a data signal to produce a first output signal. A second latch receives the first output signal and the clock signal to produce a second output signal. A third latch receives the second output signal and the clock signal to produce a third output signal. An inverter receives the third output signal to produce the data signal on a rising or falling edge of the clock signal. The first and second latches are preferably ratioed latches having series coupled pull-up and pull-down elements. The third latch is preferably a clock operated latch.