Abstract: Disclosed approaches may provide for non-blocking video processing pipelines that have the ability to efficiently share transform hardware resources. Transform hardware resources may be shared across processing parameters, such as pixel block dimensions, transform types, video stream bit depths, and/or multiple coding formats, as well as for inter-frame and intra-frame encoding. The video processing pipeline may be divided into phases, each phase having half-butterfly circuits to perform a respective portion of computations of a transform. The phases may be selectable and configurable to perform transforms for multiple different combinations of the processing parameters. In each configuration, the phases may be capable of performing a transform by a sequential pass through at least some of the phases resulting in high throughput. Approaches are also described related to improving the performance and efficiency of transpose operations of transforms.

Abstract: Disclosed approaches may provide for non-blocking video processing pipelines that have the ability to efficiently share transform hardware resources. Transform hardware resources may be shared across processing parameters, such as pixel block dimensions, transform types, video stream bit depths, and/or multiple coding formats, as well as for inter-frame and intra-frame encoding. The video processing pipeline may be divided into phases, each phase having half-butterfly circuits to perform a respective portion of computations of a transform. The phases may be selectable and configurable to perform transforms for multiple different combinations of the processing parameters. In each configuration, the phases may be capable of performing a transform by a sequential pass through at least some of the phases resulting in high throughput. Approaches are also described related to improving the performance and efficiency of transpose operations of transforms.

Abstract: A tiled graphics memory permits graphics data to be stored in different tile formats. One application is selecting a tile format optimized for the data generated for particular graphical surfaces in different rendering modes. Consequently, the tile format can be selected to optimize memory access efficiency and/or packing efficiency. In one embodiment a first tile format stores pixel data in a format storing two different types of pixel data whereas a second tile format stores one type of pixel data. In one implementation, a z-only tile format is provided to store only z data but no stencil data. At least one other tile format is provided to store both z data and stencil data. In one implementation, z data and stencil data are stored in different portions of a tile to facilitate separate memory accesses of z and stencil data.

Abstract: A raster operations (ROP) unit interleaves read and write requests for efficiently communicating with a frame buffer via a PCI Express (PCI E) link or other system bus that provides separate upstream and downstream data transfer paths. One example of a ROP unit processes pixels in groups, performing read modify writeback sequences for each group. The read requests associated with pixels in a second group are advantageously interleaved with the writeback requests for pixels in the first group prior to sending the requests on the system bus.

Abstract: A graphics system coalesces Z data and color data for a raster operations stage. The Z data and color data are stored in a memory aligned tile format. In one embodiment, rendering modes in which the tile does not have a data capacity corresponding to Z data or color data for a whole number of pixels have data for at least one pixel split across entries to improve packing efficiency. Rendering modes having a number of bits for Z data or color data that does not equal a power of two such as 24 bits, 48 bits, and 96 bits, may be implemented with a high packing efficiency in tile formats having a data capacity corresponding to a power of 2 bits.

Abstract: A graphics system coalesces Z data and color data for a raster operations stage. The Z data and color data are stored in a memory aligned tile format. In one embodiment, rendering modes in which the tile does not have a data capacity corresponding to Z data or color data for a whole number of pixels have data for at least one pixel split across entries to improve packing efficiency. Rendering modes having a number of bits for Z data or color data that does not equal a power of two such as 24 bits, 48 bits, and 96 bits, may be implemented with a high packing efficiency in tile formats having a data capacity corresponding to a power of 2 bits.

Abstract: A tiled graphics memory permits graphics data to be stored in different tile formats. One application is selecting a tile format optimized for the data generated for particular graphical surfaces in different rendering modes. Consequently, the tile format can be selected to optimize memory access efficiency and/or packing efficiency. In one embodiment a first tile format stores pixel data in a format storing two different types of pixel data whereas a second tile format stores one type of pixel data. In one implementation, a z-only tile format is provided to store only z data but no stencil data. At least one other tile format is provided to store both z data and stencil data. In one implementation, z data and stencil data are stored in different portions of a tile to facilitate separate memory accesses of z and stencil data.

Abstract: A system, method and article of manufacture are provided for retrieving information from memory. Initially, processor requests for information from a first memory are monitored. A future processor request for information is then predicted based on the previous step. Thereafter, one or more speculative requests are issued for retrieving information from the first memory in accordance with the prediction. The retrieved information is subsequently cached in a second memory for being retrieved in response to processor requests without accessing the first memory. By allowing multiple speculative requests to be issued, throughput of information in memory is maximized.