Patents by Inventor Donald A. Priore
Donald A. Priore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220206798Abstract: Systems, apparatuses, and methods for implementing scheduler queue assignment logic are disclosed. A processor includes at least a decode unit, scheduler queue assignment logic, scheduler queues, pickers, and execution units. The assignment logic receives a plurality of operations from a decode unit in each clock cycle. The assignment logic includes a separate logical unit for each different type of operation which is executable by the different execution units of the processor. For each different type of operation, the assignment logic determines which of the possible assignment permutations are valid for assigning different numbers of operations to scheduler queues in a given clock cycle. The assignment logic receives an indication of how many operations to assign in the given clock cycle, and then the assignment logic selects one of the valid assignment permutations for the number of operations specified by the indication.Type: ApplicationFiled: March 18, 2022Publication date: June 30, 2022Inventors: Matthew T. Sobel, Donald A. Priore, Alok Garg
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Patent number: 11294678Abstract: Systems, apparatuses, and methods for implementing scheduler queue assignment logic are disclosed. A processor includes at least a decode unit, scheduler queue assignment logic, scheduler queues, pickers, and execution units. The assignment logic receives a plurality of operations from a decode unit in each clock cycle. The assignment logic includes a separate logical unit for each different type of operation which is executable by the different execution units of the processor. For each different type of operation, the assignment logic determines which of the possible assignment permutations are valid for assigning different numbers of operations to scheduler queues in a given clock cycle. The assignment logic receives an indication of how many operations to assign in the given clock cycle, and then the assignment logic selects one of the valid assignment permutations for the number of operations specified by the indication.Type: GrantFiled: May 29, 2018Date of Patent: April 5, 2022Assignee: Advanced Micro Devices, Inc.Inventors: Matthew T. Sobel, Donald A. Priore, Alok Garg
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Patent number: 10896044Abstract: The techniques described herein provide an instruction fetch and decode unit having an operation cache with low latency in switching between fetching decoded operations from the operation cache and fetching and decoding instructions using a decode unit. This low latency is accomplished through a synchronization mechanism that allows work to flow through both the operation cache path and the instruction cache path until that work is stopped due to needing to wait on output from the opposite path. The existence of decoupling buffers in the operation cache path and the instruction cache path allows work to be held until that work is cleared to proceed. Other improvements, such as a specially configured operation cache tag array that allows for detection of multiple hits in a single cycle, also improve latency by, for example, improving the speed at which entries are consumed from a prediction queue that stores predicted address blocks.Type: GrantFiled: June 21, 2018Date of Patent: January 19, 2021Assignee: Advanced Micro Devices, Inc.Inventors: Marius Evers, Dhanaraj Bapurao Tavare, Ashok Tirupathy Venkatachar, Arunachalam Annamalai, Donald A. Priore, Douglas R. Williams
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Publication number: 20190391813Abstract: The techniques described herein provide an instruction fetch and decode unit having an operation cache with low latency in switching between fetching decoded operations from the operation cache and fetching and decoding instructions using a decode unit. This low latency is accomplished through a synchronization mechanism that allows work to flow through both the operation cache path and the instruction cache path until that work is stopped due to needing to wait on output from the opposite path. The existence of decoupling buffers in the operation cache path and the instruction cache path allows work to be held until that work is cleared to proceed. Other improvements, such as a specially configured operation cache tag array that allows for detection of multiple hits in a single cycle, also improve latency by, for example, improving the speed at which entries are consumed from a prediction queue that stores predicted address blocks.Type: ApplicationFiled: June 21, 2018Publication date: December 26, 2019Applicant: Advanced Micro Devices, Inc.Inventors: Marius Evers, Dhanaraj Bapurao Tavare, Ashok Tirupathy Venkatachar, Arunachalam Annamalai, Donald A. Priore, Douglas R. Williams
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Publication number: 20190369991Abstract: Systems, apparatuses, and methods for implementing scheduler queue assignment logic are disclosed. A processor includes at least a decode unit, scheduler queue assignment logic, scheduler queues, pickers, and execution units. The assignment logic receives a plurality of operations from a decode unit in each clock cycle. The assignment logic includes a separate logical unit for each different type of operation which is executable by the different execution units of the processor. For each different type of operation, the assignment logic determines which of the possible assignment permutations are valid for assigning different numbers of operations to scheduler queues in a given clock cycle. The assignment logic receives an indication of how many operations to assign in the given clock cycle, and then the assignment logic selects one of the valid assignment permutations for the number of operations specified by the indication.Type: ApplicationFiled: May 29, 2018Publication date: December 5, 2019Inventors: Matthew T. Sobel, Donald A. Priore, Alok Garg
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Patent number: 9300293Abstract: An integrated circuit device includes a first signal line for distributing a first signal. The first signal line includes a plurality of branch lines, and a leaf node is defined at an end of each branch line. First logic is coupled to the leaf nodes and operable to generate a first status signal indicative of a collective first logic state of the leaf nodes of the signal line corresponding to the first signal.Type: GrantFiled: May 14, 2013Date of Patent: March 29, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Donald A. Priore, John G. Petrovick, Jr., Stephen V. Kosonocky, Robert S. Orefice
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Publication number: 20140340114Abstract: An integrated circuit device includes a first signal line for distributing a first signal. The first signal line includes a plurality of branch lines, and a leaf node is defined at an end of each branch line. First logic is coupled to the leaf nodes and operable to generate a first status signal indicative of a collective first logic state of the leaf nodes of the signal line corresponding to the first signal.Type: ApplicationFiled: May 14, 2013Publication date: November 20, 2014Applicant: Advanced Micro Devices, Inc.Inventors: Donald A. Priore, John G. Petrovick, JR., Stephen V. Kosonocky, Robert S. Orefice
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Patent number: 8656339Abstract: A method, implemented in a processor, of determining a likelihood of failure of a circuit to be made in accordance with a circuit design, and a computer-readable storage medium storing instructions to the processor for carrying out the method. A sensitivity of a figure of merit to each variable of a plurality of variables is determined by simulating operation of the circuit using the processor. Determining the sensitivity is based on a departure of each of the variables from a respective mean value, where the variables include at least one variable derived from measurements of a fabricated component or component combination to be included in the circuit. Results from the simulation are used to predict a failure probability of the circuit to be made in accordance with the circuit design.Type: GrantFiled: December 22, 2010Date of Patent: February 18, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Kevin M. Gillespie, Timothy J. Correia, Donald A. Priore
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Patent number: 8589661Abstract: A method and apparatus are presented for processing a stream of information, including preprocessing the stream, which includes partitioning the stream into packets of interest; determining boundaries for the packets of interest, wherein a packet boundary is either a start location or an end location for a packet; and making a record of the packet boundaries by setting a hint bit in a hint bit vector, a location of the hint bit within the hint bit vector corresponding to a position of the packet in the stream. The hint bit vector is split into two or more vectors, where the hint bits are assigned to one of the vectors on an alternating basis. The packets of interest are processed corresponding to the hint bits assigned to each vector in parallel over multiple clock cycles, wherein an original order of the packets of interest is maintained in the stream.Type: GrantFiled: December 7, 2010Date of Patent: November 19, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Mike Butler, Donald A. Priore, Steven Beigelmacher
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Publication number: 20120167025Abstract: A method is disclosed of determining a likelihood of failure of a circuit made in accordance with a circuit design based on at least one variable derived from measurements of a fabricated component or component combination included in the circuit design. Also disclosed is a processor configured to perform the method and a computer-readable medium storing method instructions.Type: ApplicationFiled: December 22, 2010Publication date: June 28, 2012Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Kevin M. Gillespie, Timothy J. Correia, Donald A. Priore
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Publication number: 20120166777Abstract: Techniques for switching or parking threads in a processor including a plurality of processor cores that share a microcode engine are disclosed. In a dual-core or multi-core system, a front end, (e.g., microcode engine), of the processor cores may be shared by the two or more active threads in order to reduce the area, cost, or the like. A currently running thread may be put to a sleep state and execution of another thread may be initiated when a yield microcode command issues while the currently thread is running. The thread may be resumed on a condition that the second thread goes to a sleep state, yields, exits the processing, etc. Alternatively, a thread may be put to a sleep state when a sleep microcode command issues which is programmed to occur when the thread needs to wait for an event to occur.Type: ApplicationFiled: December 22, 2010Publication date: June 28, 2012Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Edward J. McLellan, Magiting M. Talisayon, Donald A. Priore
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Publication number: 20120144168Abstract: A method and apparatus is presented for identifying instructions in a stream of information by preprocessing the stream of information, creating a vector of instructions and breaking the vector of instructions into two or more vectors for picking the identified instructions at a high frequency.Type: ApplicationFiled: December 7, 2010Publication date: June 7, 2012Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Mike Butler, Donald A. Priore, Steven Beigelmacher
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Patent number: 7933760Abstract: A method of simulating operation of a bitcell includes determining sensitivities of a bitcell model to different component characteristics and device parameters, such as device temperature, operating voltage, and process characteristics. The determined sensitivities are normalized, so that each normalized value represents the relative sensitivity of the bitcell, under the simulated device parameters, to the component characteristic associated with the value. The normalized sensitivity values can be scaled based on a tolerance factor, and the adjusted sensitivities used to model the behavior of each component of the bitcell in subsequent simulations.Type: GrantFiled: March 25, 2008Date of Patent: April 26, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Russell Schreiber, Keith Kasprak, Donald A. Priore
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Patent number: 7647472Abstract: An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.Type: GrantFiled: August 25, 2006Date of Patent: January 12, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Thomas B. Brightman, Andrew D. Funk, David J. Husak, Edward J. McLellan, Andrew T. Brown, John F. Brown, James A. Farrell, Donald A. Priore, Mark A. Sankey, Paul Schmitt
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Publication number: 20090248383Abstract: A method of simulating operation of a bitcell includes determining sensitivities of a bitcell model to different component characteristics and device parameters, such as device temperature, operating voltage, and process characteristics. The determined sensitivities are normalized, so that each normalized value represents the relative sensitivity of the bitcell, under the simulated device parameters, to the component characteristic associated with the value. The normalized sensitivity values can be scaled based on a tolerance factor, and the adjusted sensitivities used to model the behavior of each component of the bitcell in subsequent simulations.Type: ApplicationFiled: March 25, 2008Publication date: October 1, 2009Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Russell Schreiber, Keith Kasprak, Donald A. Priore
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Publication number: 20060292292Abstract: An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.Type: ApplicationFiled: August 25, 2006Publication date: December 28, 2006Inventors: Thomas Brightman, Andrew Funk, David Husak, Edward McLellan, Andrew Brown, John Brown, James Farrell, Donald Priore, Mark Sankey, Paul Schmitt
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Patent number: 7100020Abstract: An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.Type: GrantFiled: May 7, 1999Date of Patent: August 29, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Thomas B. Brightman, Andrew T. Brown, John F. Brown, James A. Farrell, Andrew D. Funk, David J. Husak, Edward J. McLellan, Mark A. Sankey, Paul Schmitt, Donald A. Priore
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Patent number: 6807186Abstract: A single-stage grooming switch is provided for switching streams of multiplexed traffic, such as SONET STS-48, in both time and space domains. In particular, the switch implements a distributed demultiplexing architecture for switching between any input timeslot to any output timeslot at a reduced layout size. Furthermore, the distributed demultiplexing architecture results in low latencies being associated with reconfiguration of output permutations on the order of nanoseconds.Type: GrantFiled: January 17, 2002Date of Patent: October 19, 2004Assignee: LSI Logic CorporationInventors: William J. Dally, John Edmondson, Donald A. Priore, Ephrem Wu, John W. Poulton
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Publication number: 20020181482Abstract: A single-stage grooming switch is provided for switching streams of multiplexed traffic, such as SONET STS-48, in both time and space domains. In particular, the switch implements a distributed demultiplexing architecture for switching between any input timeslot to any output timeslot at a reduced layout size. Furthermore, the distributed demultiplexing architecture results in low latencies being associated with reconfiguration of output permutations on the order of nanoseconds.Type: ApplicationFiled: January 17, 2002Publication date: December 5, 2002Applicant: Velio Communications, Inc.Inventors: William J. Dally, John Edmondson, Donald A. Priore, Ephrem Wu, John W. Poulton
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Patent number: 6408401Abstract: A self-repair method for a random access memory (RAM) array comprises writing a value to the memory array, reading a value from the memory array and comparing the read and write values to identify faulty memory cells in the memory array. An address of a newly-discovered faulty memory cell is compared to at least one address of at least one previously-discovered faulty memory cell. The address of the newly discovered faulty memory cell is stored if a column or row address of the newly-discovered faulty cell does not match any column or row address, respectively, of a previously-discovered faulty memory cell. Flags are set to indicate that a spare row or a spare column must replace the row or column, respectively, identified by the address of the previously-discovered faulty memory cell, if the row or column address of the newly-discovered memory cell matches the respective row or column address of the previously-discovered faulty memory cell.Type: GrantFiled: November 13, 1998Date of Patent: June 18, 2002Assignee: Compaq Information Technologies Group, L.P.Inventors: Dilip K. Bhavsar, Donald A. Priore