Abstract: The high-speed, multi-device PCI bus communication system of the invention includes a host CPU and a chip set for connecting the host CPU to a first, low speed PCI bus. The chip set has an accelerated graphics port. A VLSI device such as a RAID cache controller includes two PCI interfaces for communicating with second and third, higher speed PCI buses, and includes an accelerated graphics interface for communicating with the accelerated graphics port. A first PCI bridge provides for communication between the accelerated graphics interface and the first PCI interface; and a second PCI bridge provides for communication between the accelerated graphics interface and the second PCI interface. A dedicated communication bus connects the accelerated graphics interface to the accelerated graphics port. A RAM port can connect the VLSI device to external RAM. The system provides for coupling multiple (e.g.

Abstract: The invention provides a PCI bridge chip for communicating command data between a primary PCI bus and a secondary PCI bus. A primary command transaction logic manages command data transfers from the primary PCI bus to the secondary PCI bus. The primary delayed transaction logic has a plurality of primary buffers for buffering command transactions to be issued on the secondary PCI bus selectively. A secondary command transaction logic manages command data transfers from the secondary PCI bus to the primary PCI bus. The second delayed transaction logic has a plurality of secondary buffers for buffering command transactions to be issued on the primary PCI bus selectively. The primary and secondary command transaction logic can for example include three buffers to buffer transaction commands in the appropriate direction. The bridge chip further provides for coupling large burst data through a memory section and to external an external RAM (or alternatively internal memory).