Abstract: A system for handling special television video features digitally. The system receives incoming broadcast video into a switch (106). The switch allows the viewer to select a main channel and at least one auxiliary channel for viewing as a special feature, if the viewer does not want to view only the main channel for that particular special feature. The main video channel data is processed by a scan converter (216) to convert it from interlaced to progressive scan. A logic device (212) handles the auxiliary channel data to format it into the selected special feature and inputs that data to the scan converter (216) such that the special feature appears in the proper place relative to the main channel image.

Abstract: A method of implementing pulse-width modulation in a display system (10, 20) that uses a spatial light modulator (SLM) (15) Each frame of data is divided into bit-planes, each bit-plane having one bit of data for each pixel of the SLM and representing a bit weight of the intensity value to be displayed by the pixels. Each bit-plane has a display time corresponding to a portion of the frame period, with bit-planes of more significant bits having longer portions. Then, the display times for one or more of the more significant bits are segmented so that the data for those bits can be displayed in segments rather than for a continuous time. (FIG. 3A). The segments are distributed throughout the frame period to reduce visual artifacts. (FIG. 3B).

Abstract: A method for expanding pulse width modulation sequences that control a display system to adapt to varying video frame times. A minimal amount of extra circuitry (10) is provided that regulates a sequencer (26). After calculating the appropriate expansion factor needed to stretch a base sequence, the system control circuit (22) sends that information to the circuitry (10). The circuitry (10) includes a counter (14) that repetitively counts down a number of clock cycles and causes the clock to drop a cycle. This dropping of clock cycles causes the sequence time to be expanded, as it takes the system longer to reach the necessary number of clock cycles that determine a sequence. Several base pulse width modulation sequences could be stored in memory, each of which can be used for a range of frame times, eliminating the need for one sequence for every possible variation in the frame time.

Abstract: A data converter (13) for providing data for secondary images in a video display system (10). One embodiment (FIG. 2) provides data for a staggered pixel array, by using an A/D converter (23) to sample the data at a rate of 2/n(h) times the sample rate of the main image, where 1/n(h) is the horizontal scaling factor. A multiplexer (24) selects between two different sample patterns. Another embodiment (FIG. 3) provides data for progressively scanned secondary images by selecting 2/n(v) times the number of lines per input field, where 1/n(v) is the vertical scaling factor.

Abstract: A method for causing a micromechanical spatial light modulator to display data for a period less than its settling time. The modulator elements receive a first pulse (40) that causes them to release from their previous state, a bias voltage is removed and reapplied, allowing the elements to move to the unaddressed state, and then the elements receive a second pulse (46). After receiving a second pulse, the elements assume an unaddressed state. In one embodiment, new address data is loaded during this unaddressed state, after which a bias is reapplied causing them to achieve the state corresponding to the new state. In another embodiment, the previous addresses are cleared during the unaddressed state, forcing the elements into an OFF state. In either embodiment, a reset pulse may be applied after either the load or clear step.

Abstract: A method of pulse width modulation using a spatial light modulator (40) with a finite transition time. The method uses m bits per sample to digitize the incoming data, but apportions the LSB times for pulse width modulation based upon m-1 bits. The current video frame displays all of the bits for each sample, except for the LSBs for each sample. The next video frame displays all of the bits for each sample, adding one more LSB for dividing up the frame time. The first frame could use either the additional LSB time and display no data, or it could use only that number of LSB times it needs. In the latter, the system will have to adjust to different partitions of the frame time for alternating frames. The system includes a spatial light modulator (40), a memory (42), a formatter (48), a sequence controller (44) and a toggle circuit (46), to perform this method.

Abstract: A DMD display system includes an inverse gamma look-up-table (50) for converting raster scanned, gamma corrected video data of 8 bits to 12 bits inverse gamma data with 8 most significant bits (msb) and 4 least significant bits (lsb). The 8 msb are coupled to the micromirror of the DMD display (10) and the four lsb are delayed and halved such that one half of the lsb is added to the next pixel in the horizontal scan and one-half of the lsb is added to the next vertical pixel one line length delayed.

Abstract: A data reformatter/frame memory (112) for efficiently orthogonally reordering a digital data stream. The disclosed reformatter/frame memory (112) is typically used in conjunction with a display device (124) for displaying the digital data, and a display controller (132) for coordinating the transfer of data between the reformatter/frame memory (112) and the display device (124). According to one embodiment, a data reformatter for a video display system includes at least one reformatter memory plane (60). The memory plane (60) comprises an input bus, an m.times.n array of memory cells (80) in communication with the input bus, and an m-bit-wide output bus. The array of memory cells (80) receives and stores m n-bit-wide input data words and outputs n m-bit-wide output data words. Each of the m-bit-wide output data words is comprised of one bit from each of the m n-bit-wide input data words.

Abstract: A SLM-based projection display system (10) samples and processes video data for delivery to a spatial light modulator (SLM) (13c), and uses a color wheel (14a) to color the SLM-generated images. A frame memory (13b) provides data to the SLM (13c) and is managed so that, if the phase of the incoming video signal changes, a desired phase relationship between the color wheel position and the data available to the SLM (13c) can be maintained. Also, a motor control unit (15a) uses a horizontal sync signal to generate a drive signal for the color wheel motor (16a), which limits the transient time during phase-changing events, and which provides a means for adjusting the phase of the drive signal.

Abstract: A method and system for improved display of digital video data. The data is arranged into bit plies according to the binary weight of each bit per pixel. The bit planes are then translated into non-binary weighted bit planes by bit translation circuitry (22). These non-binary bit planes are transmitted to the activation circuitry of a spatial light modulator array (30), such that each non-binary bit is displayed at symmetrical times around at least one predetermined point within a video frame time, eliminating visual artifacts associated with binary pulse-width modulation.

Abstract: A data reformatter/frame memory (112) for efficiently orthogonally reordering a digital data stream. The disclosed reformatter/frame memory (112) is typically used in conjunction with a display device (124) for displaying the digital data, and a display controller (132) for coordinating the transfer of data between the reformatter/frame memory (112) and the display device (124). According to one embodiment, a data reformatter for a video display system includes at least one reformatter memory plane (60). The memory plane (60) comprises an input bus, an m.times.n array of memory cells (80) in communication with the input bus, and an m-bit-wide output bus. The array of memory cells (80) receives and stores m n-bit-wide input data words and outputs n m-bit-wide output data words. Each of the m-bit-wide output data words is comprised of one bit from each of the m n-bit-wide input data words.

Abstract: A method and system for accentuating intense white display areas in sequential DMD video systems includes generating a special signal for each pixel that indicates whether to boost the intensity of that pixel in all colors. The method further includes enabling the mirrors to be turned on during times of color boundary of the color wheel such that DMD with mirrors receives different mixes of color light that are integrated together to produce intense white. The system may include degamma lookup tables for each color. The degamma lookup tables are augmented when the special signal is generated.

Abstract: A method and apparatus for synchronizing display timing in a digital television system with a pixel addressable display having a color wheel is disclosed. The display timing circuit 22 includes phase comparator 40, for comparing the phase of a wheel index signal generated by a color wheel 20 with the phase of a frame synchronization signal indicating that a complete frame is ready to be displayed. Display timing circuit 22 further comprises a color wheel synchronization generator 42 which generates a color wheel synchronization signal in response to a phase difference value produced by phase comparator 40. The color wheel synchronization signal is used to increase, decrease, or maintain the speed of color wheel 20 to achieve a known phase relationship between the frame synchronization signal and the wheel index signal. Display timing circuit 22 further comprises a clock generator applicable to generate a display master clock signal having a known frequency relation to the wheel index signal.

Abstract: A digital television system (10) is provided. System (10) may receive a video signal at composite video interface and separation circuit (16). The video signal is separated into separate video signals by composite video interface and separation circuit (16). The separate video signals are converted to digital video signals in analog to digital converter circuit (18). Line slicer (14) divides each line of digital video signal into a plurality of channels such that each channel may be processed in parallel by channel signal processors (22a) through (22d). Each channel signal processor (22a) through (22d) may provide two lines of output for each line of video input. The processed digital video signals may be formatted for displays (26a) through (26c) in formatters (24a) through (24c).

Abstract: An SLM-based digital display system (10) having a graphics display subsystem (13 and 18) for closed captioning, on-screen displays, and other graphics images that are overlaid on the video image. The graphics display subsystem (13 and 18) has a graphics processor (21) that prepares the graphics data, which is inserted into the video data path after video data processing and prior to a look-up table unit (27). A select logic unit (24) provides a control signal to a multiplexer (26) that selects between video data and graphics data for input to the look-up table unit (27). The look-up table unit (27) performs its mapping according to the type of data received, such as by linearizing video data or palletizing graphics data.

Abstract: A method of implementing pulse-width modulated image display systems (10, 20) with a spatial light modulator (SLM) (15) configured for split-reset addressing. Display frame periods are divided into time slices. Each frame of data is divided into bit-planes, each bit-plane having one bit of data for each pixel element and representing a bit weight of the intensity value to be displayed by that pixel element. Each bit-plane has a display time corresponding to a number of time slices, with bit-planes of higher bit weights being displayed for more time slices. The bit-planes are further formatted into reset groups, each reset group corresponding to a reset group of the SLM (15). The display times for reset groups of more significant bits are segmented so that the data can be displayed in segments rather than for a continuous time. During loading, segments of corresponding bit-planes are temporally aligned from one reset group to the next.

Abstract: A system (30) for packing data into a video processor is provided. System (30) comprises demultiplexer (32), first and second first in-first out buffer memories (34) and (36), and multiplexer (38). Demultiplexer (32) divides a field of video data into first and second parts (42) and (44). First and second parts (42) and (44) are stored in first first in-first out buffer memories (34) and (36), respectively. Multiplexer (38) combines one line from first first in-first out buffer memory (34) with one line from second first in-first out buffer memory (36) to form a single line for processing.

Abstract: A digital television system (10) System (10) may receive a video signal at composite video interface and separation circuit (16). The video signal is separated into component form by composite video interface and separation circuit (16). The component video signals are converted to digital component video signals in analog to digital converter circuit (18). Line slicer (14) divides each line of digital component video signal into a plurality of channels such that each channel may be processed in parallel by channel signal processors (22a) through (22d). Each channel signal processor (22a) through (22d) may provide two lines of output for each line of video input. The processed digital component video signals may be formatted for displays (26a) through (26c) in formatters (24a) through (24c). Each formatter (24a) through (24c) may comprise a plurality of first in-first out buffer memories (34a) through (34j).

Abstract: A sequential color system is provided in which a processor (22) is coupled to a memory (24) and a receiver (27). Images are generated by shining light from a light source (28) through a color wheel (30) and onto DMD array (26). Light from the DMD array (26) is shone on screen (32). By adjusting the speed and make-up of color wheel (30) color separation is greatly reduced or eliminated. Also there are techniques for sequential imaging which may be applied to other technologies, such as CRT technologies.

Abstract: A SLM-based projection display system (10) samples and processes video data for delivery to a spatial light modulator (SLM) (13c), and uses a color wheel (14a) to color the SLM-generated images. A frame memory (13b) provides data to the SLM (13c) and is managed so that, if the phase of the incoming video signal changes, a desired phase relationship between the color wheel position and the data available to the SLM (13c) can be maintained. Also, a motor control unit (15a) uses a horizontal sync signal to generate a drive signal for the color wheel motor (16a), which limits the transient time during phase-changing events, and which provides a means for adjusting the phase of the drive signal.