Patents by Inventor Donald B. Kay

Donald B. Kay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Cache self-testing technique to reduce cache test time
    Patent number: 8904227
    Abstract: A method for identifying, based on instructions stored externally to a processor containing a cache memory, a functional portion of the cache memory, then loading cache test code into the functional portion of the cache memory from an external source, and executing the cache test code stored in the cache memory to test the cache memory on a cache-line-granular basis and store fault information.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: December 2, 2014
    Assignee: Oracle International Corporation
    Inventors: Narendra Chakravarthy Nandam, Donald B. Kay
  • CACHE SELF-TESTING TECHNIQUE TO REDUCE CACHE TEST TIME
    Publication number: 20140032968
    Abstract: A method for identifying, based on instructions stored externally to a processor containing a cache memory, a functional portion of the cache memory, then loading cache test code into the functional portion of the cache memory from an external source, and executing the cache test code stored in the cache memory to test the cache memory on a cache-line-granular basis and store fault information.
    Type: Application
    Filed: July 30, 2012
    Publication date: January 30, 2014
    Inventors: Narendra Chakravarthy Nandam, Donald B. Kay
  • Dynamically reconfigurable interconnection
    Patent number: 6871294
    Abstract: A method and apparatus for dynamically reconfiguring a computing system are disclosed. The method comprises detecting a predetermined condition triggering a reconfiguration of the computing system; and dynamically reconfiguring a signal path affected by the condition from a first mode to a second mode responsive to detecting the condition. The apparatus is a computing system, comprising: a plurality of I/O switches, a crossbar switch, a plurality of signal paths; and a system controller. Each signal path is defined by an I/O switch and the crossbar switch. The system controller is capable of detecting a predetermined condition triggering a reconfiguration and dynamically reconfiguring at least one of the signal paths affected by the condition from a first mode to a second mode.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: March 22, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Andrew E. Phelps, Daniel P. Drogichen, Donald B. Kay
  • Dynamically reconfigurable interconnection
    Publication number: 20030061476
    Abstract: A method and apparatus for dynamically reconfiguring a computing system are disclosed. The method comprises detecting a predetermined condition triggering a reconfiguration of the computing system; and dynamically reconfiguring a signal path affected by the condition from a first mode to a second mode responsive to detecting the condition. The apparatus is a computing system, comprising: a plurality of I/O switches, a crossbar switch, a plurality of signal paths; and a system controller. Each signal path is defined by an I/O switch and the crossbar switch. The system controller is capable of detecting a predetermined condition triggering a reconfiguration and dynamically reconfiguring at least one of the signal paths affected by the condition from a first mode to a second mode.
    Type: Application
    Filed: September 25, 2001
    Publication date: March 27, 2003
    Inventors: Andrew E. Phelps, Daniel P. Drogichen, Donald B. Kay