Abstract: A method of conducting an assay for a set of targets, the method comprising: providing a set of targets; subjecting each target of the set of targets to a recognition event, in which each target is uniquely recognized by and bound to a recognition element associated with a code from a set of codes, thereby yielding a set of coded targets comprising the target and the recognition element; subjecting each recognition element of the set of coded targets to a transformation event, in which a molecular transformation of each recognition element produces a modified recognition element, thereby yielding a set of modified recognition elements comprising the code; subjecting each code of the set of modified recognition elements to an amplifying event, in which each code is amplified, thereby yielding a set of amplified codes; subjecting each amplified code of the set of amplified codes to a detection event, thereby determining the nucleic acid sequence of the code.

Abstract: Multiple channels of received data are processed by a multiple channel demodulation and error correction decoding engine. The statistical uncertainty of processing channels with an iterative decoder are averaged across all the channels to reduce the total processing power required of the decoding engine compared to processing each channel with a separate engine. A set of input buffers holds blocks of data for each channel needing decoding. A quality measure is computed on each input block to set the priority and iteration allocation of decoding in the common decoder. The input RF signal is digitized by a broadband tuner that processes some or all of the channels to feed the multiple channel demodulator and decoder. Multiple decoded video data streams are output.

Abstract: A system is disclosed that includes a plurality of m antenna arrays configured to receive a propagating radio frequency signal. Each antenna array includes a plurality of antenna elements and a beamformer configured to produce n different bi-directional beams using the plurality of antenna elements. The system includes a plurality of n multiple-input multiple-output transceivers (MIMO). Each MIMO transceiver includes a MIMO receiver configured to accept m received signals, wherein the i-th input signal to the j-th MIMO receiver corresponds to the j-th beam of the i-th antenna array. Each MIMO transceiver also includes a MIMO transmitter configured to provide m transmit signals, wherein the v-th output signal from the z-th MIMO transmitter corresponding to the z-th beam of the v-th antenna array is selected for transmission. m, n, v, and z are integer number values, and i=1, . . . , m, j=1, . . . , n, and v=1, . . . m.

Abstract: Multiple channels of received data are processed by a multiple channel demodulation and error correction decoding engine. The statistical uncertainty of processing channels with an iterative decoder are averaged across all the channels to reduce the total processing power required of the decoding engine compared to processing each channel with a separate engine. A set of input buffers holds blocks of data for each channel needing decoding. A quality measure is computed on each input block to set the priority and iteration allocation of decoding in the common decoder. The input RF signal is digitized by a broadband tuner that processes some or all of the channels to feed the multiple channel demodulator and decoder. Multiple decoded video data streams are output.

Abstract: A signaling approach using block repetition and phase ramping that is robust and enables multi-user communication with higher order modulations over multipath channels, coupled to a receiving approach in the time domain that utilizes phase de-ramping, block averaging and equalization.

Abstract: Multiple channels of received data are processed by a multiple channel demodulation and error correction decoding engine. The statistical uncertainty of processing channels with an iterative decoder are averaged across all the channels to reduce the total processing power required of the decoding engine compared to processing each channel with a separate engine. A set of input buffers holds blocks of data for each channel needing decoding. A quality measure is computed on each input block to set the priority and iteration allocation of decoding in the common decoder. The input RF signal is digitized by a broadband tuner that processes some or all of the channels to feed the multiple channel demodulator and decoder. Multiple decoded video data streams are output.

Abstract: A system for and method of converting successive bits of digital data into BPSK symbols using one or more BPSK symbol constellations such that orthogonal BPSK constellations are referenced to successive bits of the digital data. The system and method may toggle between referencing first and second orthogonal constellations as successive bits of the digital data are encountered. Alternatively, the system and method may successively rotate by 90° the constellation to be referenced as successive bits of the digital data are encountered. The reversal of the systems and methods described can be used to decode a transmission made by the methods described or specifically to reference a succession of orthogonal BPSK constellations to convert a succession of BPSK symbols to a succession of bits of digital data. Furthermore, a standard quadrature receiver can be used to perform the conversion.

Abstract: A simultaneous multiple channel receiver (“SMCR”) for receiving a combined signal having a plurality of carrier signals, where each carrier signal in the plurality of carriers signals corresponds to a frequency channel, and in response, simultaneously producing a plurality of output data stream signals, is disclosed. The SMCR may include a down-converter front-end capable of receiving the combined signal, a plurality of digital signal processors, wherein each digital signal processor of the plurality of digital signal processors is capable of producing an output data stream signal of the plurality of output data stream signals, and a multi-band filter in signal communication with both the down-converter front-end and the plurality of digital signal processors.

Abstract: Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A correctly decoded CRC block, indicating a decoded segment is correct with a high degree of certainty, assigns a very high confidence level to the bits in this segment and is fed back to inner and/or outer decoders (with interleaving, when appropriate) for improved iterative decoding. High confidence bits may be scattered throughout inner decoded frames to influence other bit decisions in subsequent iterations. Turbo decoders typically operate relatively well at regions where the BER is high; the invention improves iterative decoder operation at lower BERs, lowering the ‘BER floor’ that is sometimes problematic with conventional turbo decoders.

Abstract: A system for and method of converting successive bits of digital data into BPSK symbols using one or more BPSK symbol constellations such that orthogonal BPSK constellations are referenced to successive bits of the digital data. The system and method may toggle between referencing first and second orthogonal constellations as successive bits of the digital data are encountered. Alternatively, the system and method may successively rotate by 90° the constellation to be referenced as successive bits of the digital data are encountered. The reversal of the systems and methods described can be used to decode a transmission made by the methods described or specifically to reference a succession of orthogonal BPSK constellations to convert a succession of BPSK symbols to a succession of bits of digital data. Furthermore, a standard quadrature receiver can be used to perform the conversion.

Abstract: A system for and method of mapping successive bits of digital data into BPSK symbols using one or more BPSK symbol constellations such that orthogonal BPSK constellations are applied to successive bits of the digital data. The system and method may toggle between applying first and second orthogonal constellations as successive bits of the digital data are encountered. Alternatively, the system and method may successively rotate by 90° the constellation to be applied as successive bits of the digital data are encountered.

Abstract: An exemplary satellite communication system comprises a service provider unit communicably coupled to a number of subscriber units via satellite transmission. The service provider unit includes an encoder configured to encode source data into a serial transmit sequence, and is further capable of supporting at least two modes of operation. The serial transmit sequence includes a first unique word identifying a first mode of operation, and is followed by a first payload packet having a first number of channel symbols corresponding to a source packet encoded in accordance with the first mode of operation identified by the first unique word. The first payload packet is encapsulated by two unique words and the time interval between the two unique words is used to determine the first mode of operation identified by the first unique word.

Abstract: Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A correctly decoded CRC block, indicating a decoded segment is correct with a high degree of certainty, assigns a very high confidence level to the bits in this segment and is fed back to inner and/or outer decoders (with interleaving, when appropriate) for improved iterative decoding. High confidence bits may be scattered throughout inner decoded frames to influence other bit decisions in subsequent iterations. Turbo decoders typically operate relatively well at regions where the BER is high; the invention improves iterative decoder operation at lower BERs, lowering the ‘BER floor’ that is sometimes problematic with conventional turbo decoders.

Abstract: A method for estimating an SNR-related parameter, such as ES/N0, from one or more symbols. The number of symbols within a predetermined number of symbols that fall within one or more collection areas is counted. The count is then associated with a value of the SNR-related parameter. This association may be performed through one or more lookup tables. In one application, a scaling factor is derived from the count. The scaling factor may be used to scale symbols before they are quantized and inputted into a trellis decoder such as a log-MAP decoder.

Abstract: A method and apparatus for processing demodulated data comprising received symbol data is disclosed. A decoder is used to compute estimated symbols and corresponding reliability metrics. The reliability metrics are transformed into reliability weights. Optionally, residuals relating to the difference between the received symbol data and the estimated symbols are computed. Output data are generated comprising any combination of the following: estimated symbols, reliability weights, residuals, and received symbol data. The residuals may be weighted by the reliability metrics and used by demodulation or error compensation loops to instantaneously reduce or increase the bandwidth of these loops.

Abstract: A method and system are described for assigning reliability metrics to error correction coded bits or symbols that are decoded. Survivor and non-survivor paths through a portion of a trellis representation within a sliding window are determined and recorded. Primary and non-primary traceback paths through a portion of the trellis representation are determined from the recorded data. If the primary and non-primary traceback paths diverge at a release point, a reliability metric is assigned to the bit or symbol estimate corresponding to the release point. This metric is derived from the difference between the path metrics of the primary and non-primary traceback paths. Alternately, if the two paths diverge through all or a portion of a release zone, a reliability metric is assigned to the block of bit or symbol estimates corresponding to the portion or more of the release zone where the two paths diverge from one another.

Abstract: A system for MPSK symbol hypothesis testing. A received symbol having in-phase (I) and quadrature (Q) components is input to the system. Multipliers for each of the components are determined corresponding to the MPSK symbol hypothesis s being tested. The symbol s is a quadrature symbol having in-phase and quadrature components, sI and sQ, respectively. The multipliers are each derived from fractions which approximate to a desired level of resolution either ±sI or ±sQ. The system multiplies the I and Q components by their respective multipliers through a discrete series of add, shift, and twos complement operations. It then derives a metric for testing the hypothesis from the resulting products.

Abstract: An iterative system for performing carrier phase tracking of symbols using a serial turbo decoder. Estimates of a buffered block of symbols are provided by a serial turbo decoder. Optionally, reliability metrics for the estimates are provided as well. Responsive to this information, a tracking loop module determines derotation phases for each of the symbols in the buffer. A symbol derotator derotates each of the buffered symbols in the block by its corresponding derotation phase. The derotated symbols are stored back in the buffer. The process may repeat itself for a prescribed number of iterations, after which the serial turbo decoder provides estimates of the underlying source bits.

Abstract: A system for and method of mapping successive bits of digital data into BPSK symbols using one or more BPSK symbol constellations such that orthogonal BPSK constellations are applied to successive bits of the digital data. The system and method may toggle between applying first and second orthogonal constellations as successive bits of the digital data are encountered. Alternatively, the system and method may successively rotate by 90° the constellation to be applied as successive bits of the digital data are encountered.

Abstract: Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A correctly decoded CRC block, indicating a decoded segment is correct with a high degree of certainty, assigns a very high confidence level to the bits in this segment and is fed back to inner and/or outer decoders (with interleaving, when appropriate) for improved iterative decoding. High confidence bits may be scattered throughout inner decoded frames to influence other bit decisions in subsequent iterations.