Abstract: An expandable network constructed from a plurality of identical network fabric cards which uses a plurality of selected row address bits to route connection paths between adjacent columns of interconnecting switches and a software algorithm for implementing a network of any whole number power of 2 rows or ports by assigning numbers of the network switches and attached nodes are described.

Abstract: The Scalable Coherent Interface (SCI) standard of the Institute of Electrical and Electronics Engineers is intended for fast, high throughput, point-to-point, unidirectional links. It is to serve high-performance multiprocessor systems. A number of key elements are defined as part of the protocol for SCI. These include: (a) command.old which is a bit in transmitted packets for detecting stale packets to discard; (b) idle.cc which is an idle bit to be inserted between packets for detecting lost packets which toggles when the idle bit has circulated around the ringlet; and (c) idle.ac which is an idle bit which toggles when all operational nodes have had an opportunity to transmit. In addition, SCI contemplates the implementation of a number of different types of resets, including power reset, upon read or apparent loss of power for more than a second and linc reset for clearing circuits but not changing error count registers in the system.

Abstract: The Scalable Coherent Interface (SCI) standard of the Institute of Electrical and Electronics Engineers is intended for fast, high throughput, point-to-point, unidirectional links to high-performance multiprocessor systems. A system is provided for routing packets with a plurality of data bits and target identity code bits through a packet routing switching network. The packets are transmitted from source nodes through the switching network to target nodes that are designated by the target identity code bits. Operational rings are used to link output ports of switches of the output stages to input ports of switches of the input stage wherein each operational ring is identified by ring identity code bits associated with the input stage switches of the operational rings and has at least one node which is capable of performing a function with the data. Recirculation rings are used to link output ports of switches of the output stage to input ports of switches of the input stage.

Abstract: The Scalable Coherent Interface (SCI) standard of the Institute of Electrical and Electronics Engineers is intended for fast, high throughput, unidirectional links to high-performance multiprocessor systems. Key elements of the protocol for SCI include: (a) a "new/stale" bit which is generated in a data packet for detecting stale packets to discard; (b) an idle.cc which is an idle bit to be inserted between packets for detecting lost packets which toggles when the idle bit has circulated around the ringlet; and (c) a scrubber node in each operational ring of an SCI network which toggles "new/stale" bits from a "new" state to a stale state when they are received at the scrubber node. The "new/stale" bit is also set to a "new" stale bit when a packet is generated in a source node in a first operational ring for transmission to a target node in a second operational ring. A scrubber node is located as the first node of each operational ring of the network. The new/stale" bit and the idle circulation (idle.

Abstract: The Scalable Coherent Interface (SCI) standard of the Institute of Electrical and Electronics Engineers is intended for fast, high throughput, unidirectional links to high performance microprocessor systems. Key elements of the protocol for SCI include: (a) a "new/stale" bit which is generated in a data packet for detecting stale packets to discard; (b) a scrubber node in each operational ring of an SCI network which toggles "new/stale" bits from a "new" state to a stale state when they are received at the scrubber node. In addition, valid ring identity code bits are used to identify operational rings and target identity code bits are used to identify the intended designated target mode of each packet. Packets are transmitted from input ports to output ports of the switches and through operational rings of the network that are connected until each of the packets reaches a designated target node.

Abstract: The Scalable Coherent Interface (SCI) standard of the Institute of Electrical and Electronics Engineers is intended for fast, high throughput, point-to-point, unidirectional links to high-performance multiprocessor systems. Key elements of the protocol for SCI are the (a) idle.cc which are idle bits circulation to be inserted between packets transmitted in an SCI network for detecting lost packets which toggles when the idle bit circulation has circulated around the ringlet; and (b) idle.ac, or allocation bit which is a bit in a group of transmitted idle bits which toggles when all operational nodes in an SCI network have had an opportunity to transmit their data packets. All switches accumulate transitions of the allocation bits to a value that is different from the current remembered allocation value on each enabled input port. If the network is out of allocation bit synchronization at a switch when a second transition of allocation bit occurs on an input port of the switch, the transition is ignored.

Abstract: A virtual address translator comprises a content addressed memory and a word addressed memory. A task name and subsegment number from a virtual address supplied by a processor are employed as a key word to search a content addressed memory and read out a subsegment descriptor if the key word is matched. The subsegment descriptor includes an absolute base address which is added to a deflection field to obtain an absolute memory address. The memory address is applied to a memory to permit transfer of a word between the processor and the memory. The processor may present any one of several task names depending upon whether the memory reference is made for an instruction or data for the processor, or for an instruction or data for an I/O connected to the processor. Bounds, residency and access privileges are checked using the subsegment descriptor.

Abstract: A virtual address translator comprises a content addressed memory and a word addressed memory. A task name and subsegment number from a virtual address supplied by a processor are employed as a key word to search a content addressed memory and read out a subsegment descriptor if the key word is matched. The subsegment descriptor includes an absolute base address which is added to a deflection field to obtain an absolute memory address. The memory address is applied to a memory to permit transfer of a word between the processor and the memory. The processor may present any one of several task names depending upon whether the memory reference is made for an instruction or data for the processor, or for an instruction or data for an I/O connected to the processor. Bounds, residency and access privileges are checked using the subsegment descriptor.

Abstract: A virtual address translator comprises a content addressed memory and a word addressed memory. A task name and subsegment number from a virtual address supplied by a processor are employed as a key word to search a content addressed memory and read out a subsegment descriptor if the key word is matched. The subsegment descriptor includes an absolute base address which is added to a deflection field to obtain an absolute memory address. The memory address is applied to a memory to permit transfer of a word between the processor and the memory. The processor may present any one of several task names depending upon whether the memory reference is made for an instruction or data for the processor, or for an instruction or data for an I/O connected to the processor. Bounds, residency and access privileges are checked using the subsegment descriptor.