Abstract: A method and apparatus for an adjustable phase interpolator is provided. The adjustable phase interpolator includes a phase interpolator circuit that has a voltage input and a voltage output. The adjustable phase interpolator further includes a controllable capacitive load coupled to either the input or the output of the phase interpolator circuit. The controllable capacitive load is designed to add or subtract capacitance to the adjustable phase interpolator.

Abstract: A memory device includes a first memory bank and a second memory bank, each memory bank having at least one subarray of memory cells. Multiple sense amplifiers are coupled to at least one subarray of memory cells. At least one sense amplifier is configured for use by both the first memory bank and the second memory bank, but not simultaneously. The sharing of sense amplifiers between memory banks minimizes the die area penalty caused by additional memory banks. The memory device is configured such that the first memory bank is adjacent to the second memory bank.

Abstract: Delay-locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a set of delay-producing elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry.

Abstract: A memory device includes a base memory with a defective memory cell. A read circuit with a serial output port and parallel input ports is connected to the base memory. The read circuit converts parallel read data received at the parallel input ports to a first serial data stream, which is applied to the serial output port. The first serial data stream includes a faulty bit corresponding to the defective memory cell. A spare memory stores a spare bit corresponding to the defective memory cell. A bit insertion circuit is connected to the spare memory and the serial output port of the read circuit. The bit insertion circuit substitutes the faulty bit value of the first serial data stream with the spare bit.

Abstract: A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core write transaction such that the memory core write transaction has a processing time that is substantially equivalent to a memory core read transaction. The delay circuit delays the memory core write transaction for a time corresponding to the time required for signals to travel on the interconnect.

Abstract: A memory device includes a first memory bank and a second memory bank, each memory bank having at least one subarray of memory cells. Multiple sense amplifiers are coupled to both the first memory bank and the second memory bank. The multiple sense amplifiers are configured for use by both the first memory bank and the second memory bank, but not simultaneously. A control mechanism is used to avoid accessing the first memory bank and the second memory bank simultaneously. The sharing of sense amplifiers between memory banks minimizes the die area penalty caused by additional memory banks.

Abstract: A quadrature phase detector includes a first load and a current source circuit. A first differential circuit and a second differential circuit coupled to the first load. In response to a first input signal, a first switching circuit couples the current source to the first differential circuit to form a first differential amplifier. The first switching circuit also couples the current source to the second differential circuit to form a second differential amplifier. The second differential amplifier is cross-coupled to the first differential amplifier. The first and second differential amplifiers are coupled to receive a differential second input signal, wherein the first and second input signals have a substantially different signal swing. A second switching circuit couples the current source to a second load in response to the complement of the first input signal.

Abstract: A memory and method of operation is described. In one embodiment, the memory includes a group of memory cells divided into a plurality of sub-groups. Sub word-lines are selectively coupled to main word lines, each sub-word line corresponding to a sub-group and is coupled to the memory cells in the row of the corresponding sub-group. Sense amplifier circuitry is coupled to the group of memory cells. The sense amplifier circuitry is divided into a plurality of sub-sensing circuits, each of the plurality of sub-sensing circuits selectively coupled to a corresponding one of the plurality of sub-groups. The memory includes a control mechanism to control the word lines and sub-sensing circuit(s) that are activated at any one time such that only those sub-word lines and sub-sensing circuits needed to perform memory operations are operated and consume power.

Abstract: A semiconductor memory of this invention comprises a memory cell array containing memory cells arranged in matrix form, word lines each connected to all the memory cells in the same row, and bit lines each connected to all the memory cells in the same column, a shift register containing a plurality of stages of shift circuits which is used as a serial address pointer for serially specifying the addresses of actually used rows and/or columns in the memory cell array, a bypass circuit capable of forming a bypass for the shift circuit at a given stage of the shift register, and a bypass control circuit for determining whether or not a bypass is to be formed by the bypass circuit.

Abstract: A semiconductor memory device includes a silicon chip and sub-arrays formed in the chip. In each of the sub-arrays, memory cells arranged in a matrix form, word lines provided for respective rows of each of the sub-arrays, and bit lines provided for respective columns of each of the sub-arrays are arranged. Further, in the chip, amplifier groups for amplifying data read out from the memory cells are arranged for the respective sub-arrays. Amplifiers connected to respective bit lines are provided in the amplifier groups and the amplifiers each have a function of continuously holding data read out from the memory cell.