Abstract: A flash memory and a method of forming a flash memory, includes forming a polysilicon wordline on a substrate, the wordline having first and second sidewalls, the first sidewall being tapered, with respect to a surface of the substrate, to have a slope angle and the second sidewall having a slope angle greater than the slope angle of the first sidewall. Thereafter, a polysilicon spacer is formed on the second sidewall while simultaneously removing the polysilicon on the first sidewall. The polysilicon spacer forms a floating gate which is surrounded on a plurality of sides by the second sidewall.

Abstract: A photolithographic mask having a primary photolithographic mask having a pattern thereon, the pattern comprising at least two portions, each portion requiring an individual optimal energy to image the pattern, each optimal energy of each portion dissimilar to at least one of the at least two portions and a secondary photolithographic mask on at least one portion of the primary mask, the secondary mask capable of attenuating the light on at least one of the at least two portions such that the optimal energy required to image the pattern on the at least one portion is similar to another of the at least two portions.

Abstract: A wafer metrology structure for measuring both critical dimension features of multiple patterns of a semiconductor device and overlay measurements of one pattern with respect to another. The measurements are readable by a single, one-dimensional scan of a metrology system. The wafer metrology structure includes at least a first feature of a first dimension formed in a first level of the semiconductor device. The first dimension is identical to a first critical dimension of a pattern formed in the corresponding first level. A wafer metrology pattern according to the present invention also includes a second pattern of a second dimension formed in a second level of the semiconductor device. The second pattern includes an aperture superposed over the first feature. The aperture exposes at least the first feature having a critical dimension of the first pattern and thus enables a metrology system to directly measure the first feature through the aperture.

Abstract: A photolithographic method, involving the illuminating of a mask with ray angles of light, the illumination passing through an annular aperture prior to contacting the mask, the illumination passing through to the mask capable of imaging the surface below, the mask comprising a primary photolithographic mask having a pattern thereon, the pattern comprising at least two portions, each portion requiring an individual optimal energy to image the pattern, each optimal energy of each portion dissimilar to at least one of the at least two portions;

Abstract: A flash memory and a method of forming a flash memory, includes forming a polysilicon wordline on a substrate, the wordline having first and second sidewalls, the first sidewall being tapered, with respect to a surface of the substrate, to have a slope angle and the second sidewall having a slope angle greater than the slope angle of the first sidewall. Thereafter, a polysilicon spacer is formed on the second sidewall while simultaneously removing the polysilicon on the first sidewall. The polysilicon spacer forms a floating gate which is surrounded on a plurality of sides by the second sidewall.

Abstract: A flash memory and a method of forming a flash memory, includes forming a polysilicon wordline on a substrate, the wordline having first and second sidewalls, the first sidewall being tapered, with respect to a surface of the substrate, to have a slope angle and the second sidewall having a slope angle greater than the slope angle of the first sidewall. Thereafter, a polysilicon spacer is formed on the second sidewall while simultaneously removing the polysilicon on the first sidewall. The polysilicon spacer forms a floating gate which is surrounded on a plurality of sides by the second sidewall.

Abstract: Disclosed is a semiconductor structure which comprises a transistor having a source implantation and a drain implantation formed in a semiconductor substrate. The transistor further comprises a gate electrode, a gate oxide, and an active area. The source implantation and drain implantation are situated on opposite sides of said active area, and said gate oxide and gate electrode are situated on top of said active region. The transistor further comprises two trench isolations adjacent to said active area, wherein said trench isolations are situated on opposite sides of said active area such that a sidewall of each trench serves as interface to said active area, at least one of said sidewalls of said trench isolations which serves as interface to said active area being sloped having a slope between 90° and 150°, said trench isolations and source implantation and drain implantation enclosing said active area on four sides.

Abstract: Disclosed is an asymmetric field effect transistor which comprises a first region serving as source, a second region serving as drain, a thin gate oxide and a gate electrode. The gate electrode is asymmetric and one of its sidewalls is sloped. The second region extends underneath said sloped sidewall. The part of said second region which extends underneath said gate electrode is less doped than the remaining part of said second region. Furthermore, said second region has a sloped junction edge underneath said gate electrode.

Abstract: A photomask and a method for using the photomask to make dimensionally controlled resist patterns are provided. A wafer having a resist coating thereon is exposed using the mask of the invention under specially controlled defocus conditions to provide the dimensionally controlled resist pattern profile. The mask which comprises multiple phase shifter means on one side of at least one of the light shielding patterns on the mask provides light passing through the mask having multiple phases on that side of the light shielding material which produces a dimensionally controlled resist pattern profile.

Abstract: A method for monitoring a process in which a feature is formed on a substrate. A plurality of dimensions of the feature are measured using a tool. An edge width of the feature is calculated based on the plurality of dimensions. The edge width is used to determine whether the process is operating within a desired specification. The calculated edge width is compared to a baseline edge width measurement to determine a difference between them. The process is determined to be operating within the specification if the difference is less than a threshold value. If the difference is greater than or equal to the threshold value, the method determines whether the difference is caused by a change in resolution of the tool. A plurality of diagnostic measurements of the edge width may be performed. The tool is adjusted to have a respectively different focus for each respective one of the plurality of diagnostic measurements.