Abstract: A data processing system which includes a central processor unit which has an arithmetic logic unit (ALU) for performing fixed point arithmetic operations and a separate floating point unit (FPU) for performing floating point operations and which uses multi-level microcode architecture wherein each unit has its own control store (a "horizontal" store) which responds to addresses of execution control signals supplied thereto from a common control store (a "vertical" store) to produce horizontal microinstructions for performing ALU and FPU operations, respectively. Selected ones of such addresses are recognized for ALU operations by the CPU control store only, other selected ones are recognized for FPU operations by the FPU control store only, while still other selected ones are recognized for both ALU and FPU operations by both control stores so that such operations can be performed simultaneously in parallel.

Abstract: Apparatus and method is disclosed for controlling the timing of the addressing, fetching and executing of microinstructions in a data processing system such that delayed sequencing microinstructions, stretched delayed sequencing microinstructions and immediate sequencing microinstructions may be intermixed in the microinstruction stream. Circuitry is provided to determine the type of sequencing specified for each microinstruction and control the generation of the execution cycle signal and the microinstruction address clocking signal such that these signals occur in the appropriate time sequence to accomplish the specified sequencing.