Abstract: In described examples, a method for electroplating a semiconductor device includes: forming a metal foil; forming an inert anode support; attaching the metal foil to the inert anode support to form an anode; forming a cathode using a semiconductor substrate; immersing the anode and the cathode within an electrolyte solution; forming a circuit with a current source, the anode and the cathode; generating a current through the circuit; and electroplating a metal from the electrolyte solution onto the semiconductor substrate.

Abstract: In described examples, a method for electroplating a semiconductor device includes: forming a metal foil; forming an inert anode support; attaching the metal foil to the inert anode support to form an anode; forming a cathode using a semiconductor substrate; immersing the anode and the cathode within an electrolyte solution; forming a circuit with a current source, the anode and the cathode; generating a current through the circuit; and electroplating a metal from the electrolyte solution onto the semiconductor substrate.

Abstract: In described examples, a method for electroplating a semiconductor device includes: forming a metal foil; forming an inert anode support; attaching the metal foil to the inert anode support to form an anode; forming a cathode using a semiconductor substrate; immersing the anode and the cathode within an electrolyte solution; forming a circuit with a current source, the anode and the cathode; generating a current through the circuit; and electroplating a metal from the electrolyte solution onto the semiconductor substrate.

Abstract: In described examples, a method for electroplating a semiconductor device includes: forming a metal foil; forming an inert anode support; attaching the metal foil to the inert anode support to form an anode; forming a cathode using a semiconductor substrate; immersing the anode and the cathode within an electrolyte solution; forming a circuit with a current source, the anode and the cathode; generating a current through the circuit; and electroplating a metal from the electrolyte solution onto the semiconductor substrate.

Abstract: A leadframe that includes a die attachment pad and a lead having a bondwire attach portion with a thickness less than 50% of the thickness of an adjacent portion of the lead. Also a method of forming a leadframe includes forming a lead having a bond wire attach portion with an original thickness and coining the bond wire attach portion to a thickness less than 50% of the original thickness. An integrated circuit package and a method of forming an integrated circuit package are also disclosed.

Abstract: An integrated circuit package may be formed using a leadframe having an open space extending therethrough. A shunt is located within the open space such that it is not in contact with any portion of the leadframe. Tape may be applied to the lower surface of the leadframe to support the shunt and hold it in place relative to the leadframe until wirebonding and encapsulation have been completed. Thereafter, the tape may be removed.

Abstract: An integrated circuit package may be formed using a leadframe having an open space extending therethrough. A shunt is located within the open space such that it is not in contact with any portion of the leadframe. Tape may be applied to the lower surface of the leadframe to support the shunt and hold it in place relative to the leadframe until wirebonding and encapsulation have been completed. Thereafter, the tape may be removed.

Abstract: Example leadframes having both rough surfaces to enhance adhesion to molding compounds and selectively smoothed surfaces to enhance bonding wire performance, and methods to form the same are disclosed. A disclosed example packaged integrated circuit chip includes a bond wire, a leadframe having a die pad coupled to a carrier rail, and an inner lead coupled to an outer lead via a dam bar, the inner lead having a first portion having a rough surface and a second portion having a smoothed surface, a first end of the bond wire attached to the second portion of the inner lead, an integrated circuit attached to the die pad, a second end of the bond wire attached to a pad disposed on the integrated circuit, and a molding compound to encapsulate the inner lead, the integrated circuit and the bond wire.

Abstract: A palladium plated lead frame (34) for integrated circuit devices has a nickel strike (36) and a palladium/nickel alloy layer (38) separating the copper base metal (28) from the nickel intermediate layer (40) in order to prevent a galvanic potential from drawing copper ions from the base metal layer (28) to the top layer (42). The nickel strike (36) and palladium/nickel alloy layer (38) also reduce the number of paths through which a copper ion could migrate to the top surface resulting in corrosion.