Abstract: Microfluidic devices for sterilizing fluids using pulsed electric fields are disclosed. In some embodiments, a device may include first and second electrode layers and a spacer layer positioned between the electrode layers. The spacer layer may define one or more fluid channels extending between the electrode layers. A power supply may be coupled to the electrode layers and configured to supply voltage pulses to the electrode layers to generate electric field pulses within the fluid channels. In some embodiments, the electrode layers may be textured such that the electric fields generated in the fluid channels are non-uniform.

Abstract: Coated electronic components of a circuit assembly are provided, comprising: one or more lead frames, one or more chips, connection wires, a moisture barrier coating layer, and an encapsulating plastic coating layer. The moisture barrier coating layer may be applied to the electronic component with the encapsulating plastic coating layer applied on top of the moisture barrier coating layer, or vice versa; such that only lead frames are exposed. Also provided are electronic components of a circuit assembly, comprising: one or more lead frames, one or more chips, connection wires, one or more leads extending from the coated electronic component, a moisture barrier coating layer, and an encapsulating plastic coating layer. The encapsulating plastic coating layer is applied to the electronic component and the moisture barrier coating layer is applied on top of the entire encapsulating plastic coating layer on all sides, such that only the leads are exposed.

Abstract: Coated articles are provided comprising: (a) a substrate that demonstrates electrical conductivity, wherein the substrate is an electronic component of a circuit assembly; (b) a moisture barrier coating layer; and (c) an encapsulating plastic coating layer. The moisture barrier coating layer may be applied to the surface of the substrate with the encapsulating plastic coating layer applied on top of the moisture barrier coating layer, or vice versa.

Abstract: A system and method for forming an embedded chip package is disclosed. The embedded chip package includes a first chip portion having a plurality of pre-patterned re-distribution layers joined together to form a pre-patterned lamination stack, with the pre-patterned lamination stack having a die opening extending therethrough. The embedded chip package also includes a die positioned in the die opening and a second chip portion having at least one uncut re-distribution layer, with the second chip portion affixed to each of the first chip portion and the die and being patterned to be electrically connected to both of the first chip portion and the die.

Abstract: A system and method for forming a wafer level package (WLP) (i.e., wafer level chip size package) is disclosed. The WLP includes a silicon integrated circuit (IC) substrate having a plurality of die pads formed on a top surface thereof and a plurality of polymer laminates positioned thereon. Each of the polymer laminates is comprised of a separate pre-formed laminate sheet and has a plurality of vias formed therein that correspond to a respective die pad. A plurality of metal interconnects are formed on each of the plurality of polymer laminates so as to cover a portion of a top surface of a polymer laminate and extend down through the via and into contact with a metal interconnect on a neighboring polymer laminate positioned below. An input/output (I/O) system interconnect is positioned on a top surface of the wafer level package and is attached to the plurality of metal interconnects.

Abstract: High-temperature, multiple-layer polymer (MLP) capacitors with a stacked electrode arrangement are disclosed. The capacitor electrodes are separated by a polymer dielectric that is stable at high temperatures. In some embodiments, the polymer dielectric also has a high permittivity and is filled with high-permittivity nanoparticles, which enables the capacitor to achieve a very high capacitance density.

Abstract: A system and method for providing shielding to an electrical system is disclosed. A conformal shield is formed by applying a conformal insulating coating to an electrical system. A plurality of openings are formed in the insulating coating at desired locations and a first metallic layer is deposited over the insulating coating and in each of the plurality of openings, the first metallic layer being electrically connected with the circuit board at the desired locations. A second metallic layer is then deposited onto the first metallic layer to increase a thickness of the metallic layers.

Abstract: A system and method for forming an embedded chip package is disclosed. The embedded chip package includes a first chip portion having a plurality of pre-patterned re-distribution layers joined together to form a pre-patterned lamination stack, with the pre-patterned lamination stack having a die opening extending therethrough. The embedded chip package also includes a die positioned in the die opening and a second chip portion having at least one uncut re-distribution layer, with the second chip portion affixed to each of the first chip portion and the die and being patterned to be electrically connected to both of the first chip portion and the die.

Abstract: A system and method for forming a wafer level package (WLP) (i.e., wafer level chip size package) is disclosed. The WLP includes a silicon integrated circuit (IC) substrate having a plurality of die pads formed on a top surface thereof and a plurality of polymer laminates positioned thereon. Each of the polymer laminates is comprised of a separate pre-formed laminate sheet and has a plurality of vias formed therein that correspond to a respective die pad. A plurality of metal interconnects are formed on each of the plurality of polymer laminates so as to cover a portion of a top surface of a polymer laminate and extend down through the via and into contact with a metal interconnect on a neighboring polymer laminate positioned below. An input/output (I/O) system interconnect is positioned on a top surface of the wafer level package and is attached to the plurality of metal interconnects.

Abstract: A system and method for providing shielding to an electrical system is disclosed. A conformal shield is formed by applying a conformal insulating coating to an electrical system. A plurality of openings are formed in the insulating coating at desired locations and a first metallic layer is deposited over the insulating coating and in each of the plurality of openings, the first metallic layer being electrically connected with the circuit board at the desired locations. A second metallic layer is then deposited onto the first metallic layer to increase a thickness of the metallic layers.

Abstract: An integral heating and cooling unit is disclosed. The integral heating and cooling unit controls the temperature of a working fluid by heating or cooling the fluid either independently or in tandem. The integral heating and cooling unit includes a casing or outer housing, which defines a plenum. A heat exchanger pipe is attached to the outer housing and passes through the plenum. A plurality of heating elements connects to the outer housing and extends into the plenum. The heating elements heat the working fluid when they are powered and the working fluid passes through the plenum. The heat exchanger pipe extracts heat from the working fluid when a cooling fluid passes through the pipe and in heat transfer relation with the working fluid.