Abstract: A microcomputer having a 4-bit instruction register uses some double operation code (opcode) instructions thereby increasing its instruction set over the sixteen instruction limit imposed by the instruction register. During a single opcode instruction operation, a 4-bit opcode word is fetched from memory (20), is loaded into the instruction register (32), and is applied to a logic circuit (601, 603 or 621, 623). The resulting output from the logic circuit (601, 603 or 621, 623) determines the state of a latching device (610 or 630). The latching device (610 or 630) is latched into a first state in response to the output of the logic circuit, and the first opcode word stored in the instruction register controls processing of a data word to be fetched from storage. During a double opcode instruction operation, a first opcode word is fetched into the instruction register. The latching device (610 or 630) is latched into a second state in response to the output of the logic circuit.

Abstract: A Central Processing Unit provides programmable variation of the operand width for processor operations. The operands are formed with one or more N-bit segments. The CPU includes an arithmetic logic unit (ALU) which is adapted to operate serially on one N-bit segment of the operand at a time beginning with the least significant segment and repeating the operation on the remaining segments according to their order of significance. The number of repetitions of an ALU operation is controlled by a code stored in an op-code extension register (OER). The code in the OER can be changed by means of an instruction for transferring a new code to OER.

Abstract: A Central Processing Unit (CPU) provides programmable autoloading of memory pointer registers. The CPU includes an op-code extension register (OER) to store a code specifying the autoloading status of each memory pointer register. Whether or not a particular memory pointer register is loaded at the end of an instruction cycle with an operand address carried by the current instruction depends on the binary state of a particular bit position in the OER corresponding to the particular memory pointer register. The contents of the OER can be changed by means of an instruction for transferring a new code to OER. A CPU architecture having an OER permits software specification of autoloading without significantly increasing the number of op-codes required to define the instruction set. Fewer op-codes generally permit shorter instructions.

Abstract: A Central Processing Unit (CPU) provides programmable autoincrementing of memory pointer registers. The CPU includes an op-code extension register (OER) to store a code specifying the autoincrementing status of each memory pointer register. Whether or not a particular memory pointer register containing the address of an operand used in the current operation is automatically incremented at the end of an instruction cycle to contain the address of an operand required for the next operation depends on the binary state of a particular bit position in the OER corresponding to the particular memory pointer register. The contents of the op-code extension register can be changed by means of an instruction for transferring a new code to OER.

Abstract: The decoder portion of a programable logic array (PLA) includes logic devices at crosspoints defined between the word (x) lines and the address (y) lines characteristic of a decoder portion. The devices are operative to combine two or more word lines to activate a single word line in the associated read only memory (ROM) in response to one of two or more possible inputs. The technique is effective even in cases where "don't care" conditions relating the two or more possible inputs cannot be found. A substantial reduction in chip area is achieved.

Abstract: The word conductors of a semiconductor integrated ROM are foreshortened where permitted by the organization of data in the memory. The space made available by the eliminated portions of the word conductors is used for electrical connection to the bit conductors from the sides of the array rather than at the ends. A space reduction of about thirty percent is achieved.