Patents by Inventor Donald E. Cooper

Donald E. Cooper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10374000
    Abstract: A hybrid device package comprising a baseplate, a balanced composite structure (BCS) on the baseplate, a first IC on the BCS, and at least one additional IC physically coupled to the first IC. The coefficient of thermal expansion (CTE) for the stack formed from the BCS and the first IC is arranged to be approximately equal to that of the baseplate, thereby reducing the thermal stress to which the at least one additional IC is subjected when cooled to its operating temperature which might otherwise result in physical damage to the IC. The baseplate is preferably an alumina ceramic baseplate. In one embodiment, the first IC is a readout IC (ROIC), the at least one additional IC is a detector array IC which is on the ROIC, and the hybrid device package is a focal plane array (FPA).
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: August 6, 2019
    Assignee: TELEDYNE SCIENTIFIC & IMAGING, LLC
    Inventors: Donald E. Cooper, Lisa L. Fischer
  • Publication number: 20170062396
    Abstract: A tiled array of hybrid assemblies and a method of forming such an array enables the assemblies to be placed close together. Each assembly comprises first and second dies, with the second die mounted on and interconnected with the first die. Each vertical edge of a second die which is to be located adjacent to a vertical edge of another second die in the tiled array is etched such that the etched edge is aligned with a vertical edge of the first die. Indium bumps are deposited on a baseplate where the hybrid assemblies are to be mounted, and the assemblies are mounted onto respective indium bumps using a hybridizing machine, enabling the assemblies to be placed close together, preferably ?10 ?m. The first and second dies may be, for example. a detector and a readout IC, or an array of LEDs and a read-in IC.
    Type: Application
    Filed: January 13, 2016
    Publication date: March 2, 2017
    Inventors: Majid Zandian, Donald E. Cooper, Lisa L. Fischer, Victor Gil, Gerard Sullivan
  • Patent number: 9570428
    Abstract: A tiled array of hybrid assemblies and a method of forming such an array enables the assemblies to be placed close together. Each assembly comprises first and second dies, with the second die mounted on and interconnected with the first die. Each vertical edge of a second die which is to be located adjacent to a vertical edge of another second die in the tiled array is etched such that the etched edge is aligned with a vertical edge of the first die. Indium bumps are deposited on a baseplate where the hybrid assemblies are to be mounted, and the assemblies are mounted onto respective indium bumps using a hybridizing machine, enabling the assemblies to be placed close together, preferably ?10 ?m. The first and second dies may be, for example. a detector and a readout IC, or an array of LEDs and a read-in IC.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: February 14, 2017
    Assignee: TELEDYNE SCIENTIFIC & IMAGING, LLC
    Inventors: Majid Zandian, Donald E. Cooper, Lisa L. Fischer, Victor Gil, Gerard Sullivan
  • Patent number: 9520336
    Abstract: A method of improving the thermal performance of a hybrid assembly which comprises a first die, a second die, and indium bonds which bond and electrically interconnect the first die to the second die. A heat sink plate on which the hybrid assembly is to be mounted is provided. A plurality of indium bumps are deposited on the plate where the assembly is to be mounted. The bottom side of the hybrid assembly is then pressed onto the indium bumps to affix the assembly to the plate. The heat sink plate constrains the lateral coefficient of thermal expansion (CTE) of the second die such that the CTEs of the first and second dies match more closely than they would if the hybrid assembly was not mounted directly to a heat sink plate using indium bumps. The heat sink plate preferably comprises copper tungsten (CuW) or a diamond-metal composite.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: December 13, 2016
    Assignee: TELEDYNE SCIENTIFIC & IMAGING, LLC
    Inventors: Majid Zandian, Donald E. Cooper, Lisa L. Fischer, Victor Gil, Gerard Sullivan
  • Patent number: 9029259
    Abstract: A self-aligning hybridization method enabling small pixel pitch hybridizations with self-alignment and run-out protection. The method requires providing a first IC, the surface of which includes at least one electrical contact for connection to a mating IC, depositing an insulating layer on the IC's surface, patterning and etching the insulating layer to provide recesses in the insulating layer above each of the electrical contacts, and depositing a deformable conductive material in each of the recesses. A mating IC is provided which includes conductive pins positioned to align with the deformable conductive material in respective ones of the recesses on the first chip. The first and mating ICs are then hybridized by bringing the conductive pins into contact with the deformable conductive material in the recesses, such that the conductive material deforms and the pins make electrical contact with the first IC's electrical contacts.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: May 12, 2015
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventors: Philip A. Stupar, Yu-Hua K. Lin, Donald E. Cooper, Jeffrey F. DeNatale, William E. Tennant
  • Publication number: 20150083892
    Abstract: A hybrid device package comprising a baseplate, a balanced composite structure (BCS) on the baseplate, a first IC on the BCS, and at least one additional IC physically coupled to the first IC. The coefficient of thermal expansion (CTE) for the stack formed from the B CS and the first IC is arranged to be approximately equal to that of the baseplate, thereby reducing the thermal stress to which the at least one additional IC is subjected when cooled to its operating temperature which might otherwise result in physical damage to the IC. The baseplate is preferably an alumina ceramic baseplate. In one embodiment, the first IC is a readout IC (ROIC), the at least one additional IC is a detector array IC which is on the ROIC, and the hybrid device package is a focal plane array (FPA).
    Type: Application
    Filed: September 23, 2013
    Publication date: March 26, 2015
    Inventors: Donald E. Cooper, Lisa L. Fischer
  • Publication number: 20140061911
    Abstract: A self-aligning hybridization method enabling small pixel pitch hybridizations with self-alignment and run-out protection. The method requires providing a first IC, the surface of which includes at least one electrical contact for connection to a mating IC, depositing an insulating layer on the IC's surface, patterning and etching the insulating layer to provide recesses in the insulating layer above each of the electrical contacts, and depositing a deformable conductive material in each of the recesses. A mating IC is provided which includes conductive pins, preferably comprising nickel, positioned to align with the deformable conductive material in respective ones of the recesses on the first chip. The first and mating ICs are then hybridized by bringing the conductive pins into contact with the deformable conductive material in the recesses, such that the conductive material deforms and the pins make electrical contact with the first IC's electrical contacts.
    Type: Application
    Filed: November 4, 2013
    Publication date: March 6, 2014
    Applicant: TELEDYNE SCIENTIFIC & IMAGING, LLC
    Inventors: Donald E. Cooper, William E. Tennant, Robert Mihailovich
  • Patent number: 8440543
    Abstract: A method of improving thermal cycling reliability for a hybrid circuit structure requires providing at least two circuit layers, aligning two of the circuit layers vertically such that their respective circuit elements have a precise and well-defined spatial relationship, and providing an adhesive material which wicks into a portion of the space between the aligned layers so as to mitigate damage to the structure and/or interconnections that might otherwise occur due to thermal contraction mismatch between the layers. The adhesive material is required to have an associated viscosity such that, when provided under predetermined conditions, the adhesive stops wicking before reaching, and possibly degrading the performance of, the circuit elements.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: May 14, 2013
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventors: Donald E. Cooper, William E. Tennant
  • Publication number: 20130069192
    Abstract: A method of improving thermal cycling reliability for a hybrid circuit structure requires providing at least two circuit layers, aligning two of the circuit layers vertically such that their respective circuit elements have a precise and well-defined spatial relationship, and providing an adhesive material which wicks into a portion of the space between the aligned layers so as to mitigate damage to the structure and/or interconnections that might otherwise occur due to thermal contraction mismatch between the layers. The adhesive material is required to have an associated viscosity such that, when provided under predetermined conditions, the adhesive stops wicking before reaching, and possibly degrading the performance of, the circuit elements.
    Type: Application
    Filed: September 19, 2011
    Publication date: March 21, 2013
    Inventors: DONALD E. COOPER, William E. Tennant
  • Patent number: 5585624
    Abstract: A hybrid focal plane array (FPA) structure including a Balanced Composite Structure (BCS) in which several layers of materials having differing thermal expansion coefficients stabilize the FPA during cryogenic cooling. An optical substrate with a layer of an optically sensitive material detects impinging radiation. The optically sensitive material is coupled to a multiplexer (MUX) substrate via interconnection bumps. The MUX is bonded to a layer of a material having a high TEC. A rigid core layer is sandwiched between the MUX and a balancing layer formed of a material having similar mechanical and geometrical characteristics to the MUX substrate. The three-layer BCS consisting of the MUX, the rigid core layer and the balancing layer is designed to have an effective TEC matching that of the optical substrate. The bumps and the optically sensitive material are thus protected from undesirable stresses generated during thermal excursions, thereby resulting in substantially improved FPA reliability.
    Type: Grant
    Filed: March 23, 1995
    Date of Patent: December 17, 1996
    Assignee: Rockwell International Corporation
    Inventors: Rolin K. Asatourian, Winfred L. Morris, Donald E. Cooper, Michael R. James
  • Patent number: 4646765
    Abstract: A composition for adhering to human nails includes a mixture of a cyanoacrylate compound and/or graphite fibers. Such composition can take the form of either an artificial nail extender or a nail coating. The composition for forming an artificial nail includes graphite fibers, a cyanoacrylate, and a hardening accelerator containing a mixture of trichlorotrifluoroethane and N,N-dimethyl-P-toluidine. The accelerator is adapted to be sprayed onto a base material containing the graphite fibers and cyanoacrylate in the form of a mist. Nail compositions containing graphite fibers have significantly increased strength yet remain flexible to allow for flexure of the nail. The cyanoacrylate compounds increase the chemical bonding of the compositions to a nail.
    Type: Grant
    Filed: February 3, 1986
    Date of Patent: March 3, 1987
    Inventors: Donald E. Cooper, David A. Cooper
  • Patent number: 4644144
    Abstract: A document carrier envelope is particularly useful for protectively transporting checks being returned from an institution on which the check was written to the institution at which the check was deposited. The envelope is of opaque stock, thereby preserving confidentiality of the return check. The envelope is imprinted with coded indicia indicating specific financial data suitable for high speed processing. The envelope front and back panels are joined in facing contact along the margins of three edges, thereby reducing entry of air into the envelope and eliminating fouling the processing machinery. The envelope flap is notched to receive a letter opener, and the flap fold line is perforated, thereby contributing to high speed handling.
    Type: Grant
    Filed: May 13, 1985
    Date of Patent: February 17, 1987
    Inventors: Anthony R. Chandek, Leon J. Weistroffer, Donald E. Cooper, Daniel A. Bates