Patents by Inventor Donald E. Savage

Donald E. Savage has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11879185
    Abstract: Aluminum oxide (Al2O3) thin films having a high ?-phase purity and low defect density and methods for making the aluminum oxide thin films are provided. Also provided are epitaxial heterostructures that incorporate the aluminum oxide thin films as growth substrates and methods of forming the heterostructures. The Al2O3 films are pure, or nearly pure, ?-Al2O3. As such, the films contain no, or only a very low concentration of, other Al2O3 polymorph phases. In particular, the Al2O3 films contain no, or only a very low concentration of, the ?-Al2O3 polymorph phase.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: January 23, 2024
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Chang-Beom Eom, Rui Liu, Paul Gregory Evans, Donald E. Savage, Thomas Francis Kuech
  • Publication number: 20230175169
    Abstract: Aluminum oxide (Al2O3) thin films having a high ?-phase purity and low defect density and methods for making the aluminum oxide thin films are provided. Also provided are epitaxial heterostructures that incorporate the aluminum oxide thin films as growth substrates and methods of forming the heterostructures. The Al2O3 films are pure, or nearly pure, ?-Al2O3. As such, the films contain no, or only a very low concentration of, other Al2O3 polymorph phases. In particular, the Al2O3 films contain no, or only a very low concentration of, the ?-Al2O3 polymorph phase.
    Type: Application
    Filed: December 7, 2021
    Publication date: June 8, 2023
    Inventors: Chang-Beom Eom, Rui Liu, Paul Gregory Evans, Donald E. Savage
  • Patent number: 11133388
    Abstract: Semiconductor heterostructures, methods of making the heterostructures, and quantum dots and quantum computation devices based on the heterostructures are provided. The heterostructures include a quantum well of strained silicon seeded with a relatively low concentration of germanium impurities disposed between two quantum barriers of germanium or a silicon-germanium alloy. The quantum wells are characterized in that the germanium concentration in the wells has an oscillating profile that increases the valley splitting in the conduction band of the silicon quantum well.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: September 28, 2021
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Robert J. Joynt, Mark G. Friesen, Mark A. Eriksson, Susan Nan Coppersmith, Donald E. Savage
  • Publication number: 20210069999
    Abstract: Transparent, electrically conductive vanadium oxide-based perovskite films and methods of making the vanadium oxide-based perovskite films are provided. Transparent conducting vanadate perovskites are made by forming a layer of amorphous vanadate perovskite precursor around a plurality of nanoscale, crystalline, perovskite oxide seeds and heating the layer of amorphous vanadate perovskite precursor at a temperature that favors lateral vanadate perovskite crystal growth from the perovskite oxide seeds over homogeneous crystal nucleation within the layer of amorphous vanadate perovskite precursor material. The crystallization processes can form the desired vanadate perovskite phase directly or via a transformation in a controlled gas environment from an initial crystallized vanadate perovskite phase that has a higher oxidation state.
    Type: Application
    Filed: September 9, 2020
    Publication date: March 11, 2021
    Inventors: Paul Gregory Evans, Thomas Francis Kuech, Donald E. Savage, Yajin Chen, Samuel Marks
  • Patent number: 8803195
    Abstract: The present nanomembrane structures include a multilayer film comprising a single-crystalline layer of semiconductor material disposed between two other single-crystalline layers of semiconductor material. A plurality of holes extending through the nanomembrane are at least partially, and preferably entirely, filled with a filler material which is also a semiconductor, but which differs from the nanomembrane semiconductor materials in composition, crystal orientation, or both.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: August 12, 2014
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Max G. Lagally, Shelley A. Scott, Donald E. Savage
  • Patent number: 7973336
    Abstract: Growth of multilayer films is carried out in a manner which allows close control of the strain in the grown layers and complete release of the grown films to allow mounting of the released multilayer structures on selected substrates. A layer of material, such as silicon-germanium, is grown onto a template layer, such as silicon, of a substrate having a sacrificial layer on which the template layer is formed. The grown layer has a lattice mismatch with the template layer so that it is strained as deposited. A top layer of crystalline material, such as silicon, is grown on the alloy layer to form a multilayer structure with the grown layer and the template layer. The sacrificial layer is preferentially etched away to release the multilayer structure from the sacrificial layer, relaxing the grown layer and straining the crystalline layers interfaced with it.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: July 5, 2011
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Donald E. Savage, Michelle M. Roberts, Max G. Lagally
  • Publication number: 20090032842
    Abstract: The present nanomembrane structures include a multilayer film comprising a single-crystalline layer of semiconductor material disposed between two other single-crystalline layers of semiconductor material. A plurality of holes extending through the nanomembrane are at least partially, and preferably entirely, filled with a filler material which is also a semiconductor, but which differs from the nanomembrane semiconductor materials in composition, crystal orientation, or both.
    Type: Application
    Filed: March 10, 2008
    Publication date: February 5, 2009
    Inventors: Max G. Lagally, Shelley A. Scott, Donald E. Savage
  • Publication number: 20080296615
    Abstract: Growth of multilayer films is carried out in a manner which allows close control of the strain in the grown layers and complete release of the grown films to allow mounting of the released multilayer structures on selected substrates. A layer of material, such as silicon-germanium, is grown onto a template layer, such as silicon, of a substrate having a sacrificial layer on which the template layer is formed. The grown layer has a lattice mismatch with the template layer so that it is strained as deposited. A top layer of crystalline material, such as silicon, is grown on the alloy layer to form a multilayer structure with the grown layer and the template layer. The sacrificial layer is preferentially etched away to release the multilayer structure from the sacrificial layer, relaxing the grown layer and straining the crystalline layers interfaced with it.
    Type: Application
    Filed: May 8, 2007
    Publication date: December 4, 2008
    Inventors: Donald E. Savage, Michelle M. Roberts, Max G. Lagally
  • Patent number: 7229901
    Abstract: Growth of multilayer films is carried out in a manner which allows close control of the strain in the grown layers and complete release of the grown films to allow mounting of the released multilayer structures on selected substrates. A layer of material, such as silicon-germanium, is grown onto a template layer, such as silicon, of a substrate having a sacrificial layer on which the template layer is formed. The grown layer has a lattice mismatch with the template layer so that it is strained as deposited. A top layer of crystalline material, such as silicon, is grown on the alloy layer to form a multilayer structure with the grown layer and the template layer. The sacrificial layer is preferentially etched away to release the multilayer structure from the sacrificial layer, relaxing the grown layer and straining the crystalline layers interfaced with it.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: June 12, 2007
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Donald E. Savage, Michelle M. Roberts, Max G. Lagally
  • Patent number: 6597010
    Abstract: Semiconductor dot devices include a multiple layer semiconductor structure having a substrate, a back gate electrode layer, a quantum well layer, a tunnel barrier layer between the quantum well layer and the back gate, and a barrier layer above the quantum well layer. Multiple electrode gates are formed on the multi-layer semiconductor with the gates spaced from each other by a region beneath which quantum dots may be defined. Appropriate voltages applied to the electrodes allow the development and appropriate positioning of the quantum dots, allowing a large number of quantum dots be formed in a series with appropriate coupling between the dots.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: July 22, 2003
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Mark A. Eriksson, Mark G. Friesen, Robert J. Joynt, Max G. Lagally, Daniel W. van der Weide, Paul Rugheimer, Donald E. Savage
  • Publication number: 20020179897
    Abstract: Semiconductor dot devices include a multiple layer semiconductor structure having a substrate, a back gate electrode layer, a quantum well layer, a tunnel barrier layer between the quantum well layer and the back gate, and a barrier layer above the quantum well layer. Multiple electrode gates are formed on the multi-layer semiconductor with the gates spaced from each other by a region beneath which quantum dots may be defined. Appropriate voltages applied to the electrodes allow the development and appropriate positioning of the quantum dots, allowing a large number of quantum dots be formed in a series with appropriate coupling between the dots.
    Type: Application
    Filed: March 8, 2002
    Publication date: December 5, 2002
    Inventors: Mark A. Eriksson, Mark G. Friesen, Robert J. Joynt, Max G. Lagally, Daniel W. van der Weide, Paul Rugheimer, Donald E. Savage