Patents by Inventor Donald E. Savage

Donald E. Savage has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8803195
    Abstract: The present nanomembrane structures include a multilayer film comprising a single-crystalline layer of semiconductor material disposed between two other single-crystalline layers of semiconductor material. A plurality of holes extending through the nanomembrane are at least partially, and preferably entirely, filled with a filler material which is also a semiconductor, but which differs from the nanomembrane semiconductor materials in composition, crystal orientation, or both.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: August 12, 2014
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Max G. Lagally, Shelley A. Scott, Donald E. Savage
  • Patent number: 7973336
    Abstract: Growth of multilayer films is carried out in a manner which allows close control of the strain in the grown layers and complete release of the grown films to allow mounting of the released multilayer structures on selected substrates. A layer of material, such as silicon-germanium, is grown onto a template layer, such as silicon, of a substrate having a sacrificial layer on which the template layer is formed. The grown layer has a lattice mismatch with the template layer so that it is strained as deposited. A top layer of crystalline material, such as silicon, is grown on the alloy layer to form a multilayer structure with the grown layer and the template layer. The sacrificial layer is preferentially etched away to release the multilayer structure from the sacrificial layer, relaxing the grown layer and straining the crystalline layers interfaced with it.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: July 5, 2011
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Donald E. Savage, Michelle M. Roberts, Max G. Lagally
  • Publication number: 20090032842
    Abstract: The present nanomembrane structures include a multilayer film comprising a single-crystalline layer of semiconductor material disposed between two other single-crystalline layers of semiconductor material. A plurality of holes extending through the nanomembrane are at least partially, and preferably entirely, filled with a filler material which is also a semiconductor, but which differs from the nanomembrane semiconductor materials in composition, crystal orientation, or both.
    Type: Application
    Filed: March 10, 2008
    Publication date: February 5, 2009
    Inventors: Max G. Lagally, Shelley A. Scott, Donald E. Savage
  • Publication number: 20080296615
    Abstract: Growth of multilayer films is carried out in a manner which allows close control of the strain in the grown layers and complete release of the grown films to allow mounting of the released multilayer structures on selected substrates. A layer of material, such as silicon-germanium, is grown onto a template layer, such as silicon, of a substrate having a sacrificial layer on which the template layer is formed. The grown layer has a lattice mismatch with the template layer so that it is strained as deposited. A top layer of crystalline material, such as silicon, is grown on the alloy layer to form a multilayer structure with the grown layer and the template layer. The sacrificial layer is preferentially etched away to release the multilayer structure from the sacrificial layer, relaxing the grown layer and straining the crystalline layers interfaced with it.
    Type: Application
    Filed: May 8, 2007
    Publication date: December 4, 2008
    Inventors: Donald E. Savage, Michelle M. Roberts, Max G. Lagally
  • Patent number: 7229901
    Abstract: Growth of multilayer films is carried out in a manner which allows close control of the strain in the grown layers and complete release of the grown films to allow mounting of the released multilayer structures on selected substrates. A layer of material, such as silicon-germanium, is grown onto a template layer, such as silicon, of a substrate having a sacrificial layer on which the template layer is formed. The grown layer has a lattice mismatch with the template layer so that it is strained as deposited. A top layer of crystalline material, such as silicon, is grown on the alloy layer to form a multilayer structure with the grown layer and the template layer. The sacrificial layer is preferentially etched away to release the multilayer structure from the sacrificial layer, relaxing the grown layer and straining the crystalline layers interfaced with it.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: June 12, 2007
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Donald E. Savage, Michelle M. Roberts, Max G. Lagally
  • Patent number: 6597010
    Abstract: Semiconductor dot devices include a multiple layer semiconductor structure having a substrate, a back gate electrode layer, a quantum well layer, a tunnel barrier layer between the quantum well layer and the back gate, and a barrier layer above the quantum well layer. Multiple electrode gates are formed on the multi-layer semiconductor with the gates spaced from each other by a region beneath which quantum dots may be defined. Appropriate voltages applied to the electrodes allow the development and appropriate positioning of the quantum dots, allowing a large number of quantum dots be formed in a series with appropriate coupling between the dots.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: July 22, 2003
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Mark A. Eriksson, Mark G. Friesen, Robert J. Joynt, Max G. Lagally, Daniel W. van der Weide, Paul Rugheimer, Donald E. Savage
  • Publication number: 20020179897
    Abstract: Semiconductor dot devices include a multiple layer semiconductor structure having a substrate, a back gate electrode layer, a quantum well layer, a tunnel barrier layer between the quantum well layer and the back gate, and a barrier layer above the quantum well layer. Multiple electrode gates are formed on the multi-layer semiconductor with the gates spaced from each other by a region beneath which quantum dots may be defined. Appropriate voltages applied to the electrodes allow the development and appropriate positioning of the quantum dots, allowing a large number of quantum dots be formed in a series with appropriate coupling between the dots.
    Type: Application
    Filed: March 8, 2002
    Publication date: December 5, 2002
    Inventors: Mark A. Eriksson, Mark G. Friesen, Robert J. Joynt, Max G. Lagally, Daniel W. van der Weide, Paul Rugheimer, Donald E. Savage